Oscillators – Solid state active element oscillator – Transistors
Reexamination Certificate
1999-06-22
2001-04-10
Kinkead, Arnold (Department: 2817)
Oscillators
Solid state active element oscillator
Transistors
C331S057000, C331S17700V, C327S261000, C327S264000, C327S266000, C327S270000
Reexamination Certificate
active
06215368
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a voltage controlling/oscillating device in which the frequency of oscillation varies according to the voltage for controlling the frequency.
BACKGROUND OF THE INVENTION
FIG. 14
is a block diagram showing configuration of a voltage controlling/oscillating device based on the conventional technology. This voltage controlling/oscillating device
1
comprises a delay unit
11
, a delay interpolator
12
, and an inverting gate
13
. A signal outputted from the output terminal OUT
1
of the delay interpolator
12
is finally outputted from an output terminal
15
of the voltage controlling/oscillating device
1
to an external device as a clock signal CLK. The same signal as the output signal is also inputted into the inverting gate
13
. The signal inputted into the inverting gate
13
is inputted with the phase thereof inverted into a first input terminal FST
1
of the delay interpolator
12
and delay unit
11
. The signal inputted into the delay unit
11
is delayed by a preset delay rate d
1
and inputted into a second input terminal SLW
1
of the delay interpolator
12
. An oscillation frequency control voltage (Namely, a voltage for controlling the oscillation frequency) VCTL is inputted into a control terminal CTL
1
of the delay interpolator
12
through an oscillation frequency control terminal
14
of the voltage controlling/oscillating device
1
.
FIG. 15
is a circuit diagram showing detailed configuration of the voltage controlling/oscillating device
1
. The delay unit
11
comprises four pieces of first to fourth transistors
101
,
102
,
103
, and
104
; three pieces of first to third current sources
105
,
106
, and
107
; two pieces of resistors
108
and
109
; and two pieces of capacitors
110
and
111
, and constitute a differential switching circuit and an emitter follower. The circuit constant of the delay unit
11
is designed in such a way that a propagation delay between input and output thereof will be a desired delay rate d
1
.
The first transistor
101
of the differential switching circuit is connected to an input terminal IN of the delay unit
11
at the base terminal thereof, the collector terminal thereof is connected to a power supply terminal VCC through the loading resistor
108
, and the emitter terminal thereof is connected to the first current source
105
. The second transistor
102
of the differential switching circuit is connected to an inverting input terminal /IN (expressed with a bar over IN in the figure) of the delay unit
11
at the base terminal thereof, the collector terminal thereof is connected to the power supply terminal VCC through the loading resistor
109
, and the emitter terminal thereof is connected to the first current source
105
. The collector terminal of the first transistor
101
is connected to one electrode of the capacitor
110
and the collector terminal of the second transistor
102
is connected to one electrode of the capacitor
111
, and the other electrodes of these capacitors are connected to the power supply terminal VCC. It should be noted that the symbol “/” in front of a terminal symbol in this specification represents that an inverted signal of an input or an output signal to a terminal with the same terminal symbol is inputted or outputted.
The collector terminal of the second transistor
102
is connected to the base terminal of the third transistor
103
of the emitter follower. In the third transistor
103
, the collector terminal is connected to the power supply terminal VCC, and the emitter terminal is connected to the second current source
106
as well as to the output terminal OUT of the delay unit
11
. The collector terminal of the first transistor
101
is connected to the base terminal of the fourth transistor
104
as the emitter follower. In the fourth transistor
104
, the collector terminal is connected to the power supply terminal VCC, and the emitter terminal is connected to the third power supply terminal
107
as well as to the inverting output terminal /OUT of the delay unit
11
. The output terminal /OUT and inverting output terminal /OUT of the delay unit
11
are connected to the second input terminal SLW
1
and second inverting input terminal /SLW
1
of the delay interpolator
12
respectively.
Herein, it is assumed that waveforms of signals inputted into the first input terminal FST
1
and the second input terminal SLW
1
of the delay interpolator
12
are Vfst (t) and Vslw (t); each input resistance, input capacity and delay constant of the first and second transistors
101
and
102
are rb, Cdif, and Kdif respectively. Further, it is assumed that each input capacity and delay constant of the third and fourth transistors
103
and
104
are Ceh and Keh respectively; and a cutoff angle frequency of the transistor is &ohgr;t. Also, it is assumed that the resistance of the resistors
108
and
109
is RL. Further, it is assumed that the current of the first current source
105
is IEE
0
, and the current of the second and third current sources
106
and
107
is IEE
1
. Then, the propagation delay d
1
in the delay unit
11
can be expressed with the help of the following Equation (1).
d
1
=
V
slw(
t
)−
V
fst(
t
)=
rb
/(
RL·&ohgr;t
)+
rb·C
dif+
In
(2)·
RL·Ceh=rb
/(
RL·&ohgr;t
)+
rb·K
dif·
IEE
0
+
In
(2)·
RL·Keh·IEE
1
(1)
The first term and second term in the right side of this Equation (1) corresponds to a switching delay rate in the pair of differential transistors respectively, and the third term therein corresponds to a propagation delay rate in the emitter follower.
The delay interpolator
12
comprises eight pieces of the fifth to twelfth transistors
201
,
202
,
203
,
204
,
205
,
206
,
207
, and
208
; three pieces of the fourth to sixth current sources
209
,
210
, and
211
; four pieces of resistors
212
,
213
,
214
, and
215
; and two pieces of capacitors
216
and
217
, which constitute a current distributing circuit, a differential switching circuit, and an emitter follower. The circuit constant of the delay interpolator
12
is designed in such a way that a propagation delay between input and output thereof will be a desired delay rate d
2
.
In the fifth transistor
201
of the current distributing circuit, the base terminal is connected to a control terminal CTL
1
of the delay interpolator
12
, and the emitter terminal is connected to the fourth current source
209
through the resistor
212
. In the sixth transistor
202
of the current distributing circuit, the base terminal is connected to an inverting control terminal /CTL
1
of the delay interpolator
12
, and the emitter terminal thereof is connected to the fourth current source
209
through the resistor
213
.
In the seventh transistor
203
of the differential switching circuit, the base terminal is connected to the second input terminal SLW
1
of the delay interpolator
12
, the collector terminal is connected to the power supply terminal VCC through the loading resistor
214
, and the emitter terminal is connected to the collector terminal of the fifth transistor
201
. In the eighth transistor
204
of the differential switching circuit, the base terminal is connected to the second inverting input terminal /SLW
1
of the delay interpolator
12
, the collector terminal thereof is connected to the power supply terminal VCC through the loading resistor
215
, and the emitter terminal is connected to the collector terminal of the fifth transistor
201
.
In the ninth transistor
205
of the differential switching circuit, the base terminal is connected to the first input terminal FST
1
of the delay interpolator
12
, the collector terminal is connected to the collector terminal of the seventh transistor
203
, and the emitter terminal is connected to the collector terminal of the sixth transistor
202
. In the tenth transistor
206
of the differential switching circuit, the base terminal is connected to the first inverting input terminal /FST
1
of the delay interpolator
Motoshima Kuniaki
Tagami Hitoyuki
Kinkead Arnold
Mitsubishi Denki & Kabushiki Kaisha
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