Voltage controlled delay loop with central interpolator

Details Voltage controlled delay loop with central interpolator Voltage controlled delay loop with central interpolator

2007-03-13

2007-03-13

Nguyen, Linh My (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S153000

Reexamination Certificate

active

10999889

ABSTRACT:
A voltage controlled delay loop and method are disclosed for clock and data recovery applications. The voltage controlled delay loop generates clock signals having similar frequency and different phases. The voltage controlled delay loop comprises at least one delay element to generate at least two phases of a reference clock; a central interpolator for interpolating the at least two phases of the reference clock to generate an interpolated signal; and an input that injects the interpolated signal into a delay stage. The central interpolator provides a fine phase control. In addition, a coarse phase control can optionally be achieved by selectively injecting the interpolated signal into a given delay stage. A further voltage controlled delay loop is disclosed with coarse and fine phase control using a number of interpolators.

REFERENCES:
patent: 6281726 (2001-08-01), Miller, Jr.
patent: 6650157 (2003-11-01), Amick et al.
patent: 2004/0076192 (2004-04-01), Zerbe et al.
patent: 2005/0278131 (2005-12-01), Rifani et al.
patent: WO 97/14214 (1997-04-01), None

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