Voltage-controlled delay line, direct phase controlled voltage-c

Details Voltage-controlled delay line, direct phase controlled voltage-c Voltage-controlled delay line, direct phase controlled voltage-c

1998-03-18

2000-12-26

Chin, Stephen

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

327150, 327153, 327158, 327159, 327270, 327271, 375327, 375328, 375375, 375376, H03L 707

Patent

active

06166572&

ABSTRACT:
A clock/data recovery device employs a phase-locked loop that supplies a single clock signal and a control voltage signal to at least one clock/data recovery circuit. The clock/data recovery circuit has a voltage-controlled delay line or direct phase controlled voltage-controlled oscillator that generates a multiple-phase clock signal, which is used to recover a clock signal and data from a received data signal. The voltage-controlled delay line or direct phase controlled vottage-controlled oscillator has a cascade or ring of voltage controlled logic gates, with propagation delays controlled by the control voltage signal from the phase-locked loop, and additional logic gates that supply the clock signal from the phase-locked loop to a selectable one of the voltage-controlled logic gates.

REFERENCES:
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patent: 5838204 (1998-11-01), Yao
patent: 5901190 (1999-05-01), Lee
patent: 5963074 (1999-10-01), Arkin
Dao-Long Chen, "A Power and Area Efficient CMOS Clock/Data Recovery Circuit for High-Speed Serial Interfaces", IEEE Journal of Solid-State Circuits , Aug. 1996, pp. 1171-1176.

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