Voltage controlled delay element

Details Voltage controlled delay element Voltage controlled delay element

1990-11-14

1992-06-09

Hudspeth, David

Electrical transmission or interconnection systems

With nonswitching means responsive to external nonelectrical...

Temperature responsive

307594, 307597, 307246, H03K 513, H03K 1756

Patent

active

051210150

ABSTRACT:
A BICMOS voltage controllable delay element has an input terminal that is supplied with an input voltage from a pair of BICMOS transmission gates. The input voltage is either a control voltage or a reference voltage as determined by the state of an input signal. A first BICMOS inverter is switched by the input voltage and the charge and discharge of a timing capacitor is controlled by the magnitude of the control voltage and the reference voltage. A second BICMOS inverter responds to the timing capacitor voltage for developing an output signal voltage that is phase delayed with respect to the input signal voltage. A precision delay element using a PLL circuit is shown as are a frequency multiplier arrangement and a pulse width measuring arrangement.

REFERENCES:
patent: 4591745 (1986-05-01), Shen
patent: 4746822 (1988-05-01), Mahoney
patent: 4797579 (1989-01-01), Lewis
patent: 4812679 (1989-03-01), Mahabadi
patent: 4894791 (1990-01-01), Jiang et al.

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