Voltage-controlled delay circuit using second-order phase...

Details Voltage-controlled delay circuit using second-order phase... Voltage-controlled delay circuit using second-order phase...

2003-10-30

2009-06-09

Nguyen, Long (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Phase shift by less than period of input

C327S256000, C327S158000

Reexamination Certificate

active

07545193

ABSTRACT:
Phase interpolation techniques for voltage-controlled delay line (VCDL) implementation are provided. The techniques of the invention may employ a second-order phase interpolation topology to improve tuning range performance of the VCDL over process and temperature variation. In one aspect of the invention, the technique may use a complementary input signal to set an absolute 180-degree phase reference. As a result, the maximum tuning range of 180 degrees can be achieved regardless of internal delay variation.

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S. Lee et al., “A 5 Gb/s 0.25 μm CMOS Jitter-Tolerant Variable-Interval Oversampling Clock/Data Recovery Circuit,” ISSCC, Session 15, Gigabit Communications, pp. 463-465, Feb. 2002.
J. Savoj et al., “A 10-Gb/s CMOS Clock and Data Recovery Circuit with a Half-Rate Linear Phase Detector,” IEEE Journal of Solid-State Circuits, vol. 36, No. 5, pp. 761-767, May 2001.
W. Rhee, “A Low Power, Wide Linear-Range CMOS Voltage-Controlled Oscillator,” Proc. of IEEE, pp. II-85-II-88, May 1998.

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