Voltage controlled delay circuit

Details Voltage controlled delay circuit Voltage controlled delay circuit

2000-09-22

2003-01-14

Le, Dinh T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

C331S057000

Reexamination Certificate

active

06507229

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-271252, filed Sep. 24, 1999, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to a voltage controlled delay circuit and, more particularly, to a voltage controlled delay circuit using single-ended delay circuits which is, for example, used in a ring oscillator for a voltage controlled oscillator (VCO) in a phase-locked loop (PLL) circuit, and a voltage controlled delay line (VCDL).
When a ring oscillator is composed by connecting a plurality of delay elements each as a stage in the form of a loop as a VCO of a PLL circuit, there are some points to which care should be exercised in design. It is important from this point of view to decrease a phase error due to a random noise generated in a delay element and to decrease a phase error due to a variation in power supply potential. VCC/ground potential GND.
Recently, since a scale of a LSI (large scale integrated circuit) is further extended and an operation frequency therein is improved, it is not expected much to sufficiently suppress a potential variation in VCC/GND. Therefore it has been known that as a main cause of the occurrence of jitter (fluctuation of an edge of an output signal) in PLL output frequency, an effect of the voltage variation in VCC/GND is dominant more than that of the random noise.
Hence, in a PLL circuit, a differential delay circuit is used more often as a delay element of a VCO that is a core thereof. The use of the differential delay circuit improves a PSRR (Power Supply Reduction Ratio) that is an index indicative of an extent of an effect of potential variation in VCC/GND, and also enables the jitter in PLL output frequency to be reduced to a low level.
The demand for improving the operation frequency is, however, further increased, and in proportion to the demand, it is required to further decrease a level of the jitter required for the PLL and VCDL. Therefore, the differential delay circuit has been contrived also in various ways.
However in the differential delay circuit, since random noises generated in the elements are great as compared to the single-ended delay circuit and voltage amplitude is not increased so much, there are some problems that contribution of the noises to a phase error is greater than that in the single-ended delay circuit, and that it is necessary to pile up some stages of transistors in the vertical direction in order to keep constant current characteristics. These problems become more remarkable as elements are made finer and power supply voltage is further decreased in accordance with the progress of process techniques, so that a circuit design may has further difficulty.
Regarding the aforementioned points, since it is easy to obtain a low-voltage design in a single-ended delay circuit, it is known that the single-ended delay circuit is effective in solving the above problems if the problem of PSRR is only solved, and a VCO contrived in such a way is mounted, for example, on a microprocessor.
FIG. 6
illustrates an example of conventional VCO comprised of push-pull inverter delay circuits.
In
FIG. 6
, A P
0
is a PMOS transistor (P-MOS transistor) for current supply in which a source is connected to a VCC node and a delay time amount control voltage Vcntrl is applied to a gate. Each of IV
1
to IV
3
is a push-pull inverter delay circuit connected between a drain node of the above PMOS transistor P
0
and GND, and is connected in the form of a loop as an entire configuration to compose a ring oscillator. A decoupling capacitor Cd is connected between the drain node of the PMOS transistor P
0
and GND. An output signal of the ring oscillator is output to a latter-stage circuit with the VCC shifted from an “H” level by a level shift circuit
60
.
In the VCO illustrated in
FIG. 6
, in the case where the decoupling capacitor Cd is not connected, when the power supply voltage VCC varies, a circuit threshold and driving capability of each of the push-pull inverter delay circuits IV
1
to IV
3
as a push-pull stage vary, and an oscillation frequency changes.
That is, since a supply source of the control voltage Vcntrl is strongly coupled to the VCC node via capacity between the source and gate of the PMOS transistor P
0
for current supply, for example, when the VCC is decreased, the control voltage Vcntrl is decreased following the decrease of the VCC, and a difference between the control voltage Vcntrl and VCC becomes little.
However, a potential of the drain node of the PMOS transistor P
0
for current supply changes, and in sensitively response to the change in the potential, a delay time amount in each of the delay circuits IV
1
to IV
3
changes, and the oscillation frequency changes considerably.
Therefore, by connecting the decoupling capacitor Cd, it is possible to fairly suppress the variation in the potential of the drain node of the PMOS transistor P
0
for current supply and to improve the PSRR.
Meanwhile, when the capacity of the decoupling capacitor Cd is excessively great, the voltage between the drain and source of the PMOS transistor P
0
for current supply changes, a current supplied from the PMOS transistor P
0
for current supply changes, and as a result the oscillation frequency changes to some extent and thereby becomes unstable.
In contrast to the foregoing, when the capacity of the decoupling capacitor Cd is excessively small, the effect for improving the PSRR deteriorates, and the performance of the PLL circuit is not improved more than some extent.
Accordingly as described above, the above-mentioned push-pull inverter delay circuits IV
1
to IV
3
have characteristics that their delay times strongly depend on the power supply voltage VCC, and therefore there is a problem that it is necessary to suppress the variation in the power supply voltage VCC in order to reduce the jitter.
As described above, in the conventional VCO provided by connecting a decoupling capacitor to a ring oscillator comprised of push-pull inverter delay circuits connected in the form of a loop, there is a problem that the capacity setting in the decoupling capacitor is difficult, and that sufficient performance is not always obtained.
BRIEF SUMMARY OF THE INVENTION
The present invention is carried out to solve the above-mentioned problems. It is an object of the present invention to provide a voltage controlled delay circuit capable of improving a PSRR with a simple configuration without connecting a decoupling capacitor, and of improving performance of a circuit applying the delay circuit.
The voltage controlled delay circuit according to the present invention comprises a plurality of inverter delay circuits connected in series (cascade), a second MOS transistor of second-conductive-type and a push-pull inverter circuit. Each of the inverter delay circuits has a MOS transistor of first-conductive-type having a drain-source pass connected to a first power supply node and a gate to which a delay time amount control voltage is applied, a first MOS transistor of second-conductive-type having a drain-source pass connected at its one end to the other end of the drain-source pass of the MOS transistor of first-conductive-type, an input node connected to the gate of the first MOS transistor, of second-conductive-type, and an output node connected between the drain-source passes of the MOS transistor of first-conductive-type and the first MOS transistor of second-conductive-type. The input node of each of the inverter delay circuits except an inverter delay circuit of a first stage is connected to the output node of another inverter delay circuit of a former stage.
The second MOS transistor of second-conductive-type has a drain-source pass connected between a common connection node to which the other end of the drain-source pass of each first MOS transistor of second-conductive-type is commonly connected and a second power supply node, and a gate to which a

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