Voltage-controlled capacitive element and semiconductor...

Details Voltage-controlled capacitive element and semiconductor... Voltage-controlled capacitive element and semiconductor...

2007-05-01

2007-05-01

Dickey, Thomas L. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

Passive components in ics

C257S313000

Reexamination Certificate

active

10819123

ABSTRACT:
An N well is disposed in the upper surface of a P type substrate, a gate insulating film and a gate electrode are disposed thereon, and the gate electrode is connected to a gate terminal. Two p+diffusion regions are placed in two areas in the surface of the N well sandwiching the gate electrode, and the p+diffusion regions are connected to a ground potential wiring. Further, an n+diffusion region is disposed in the surface of the N well, and is connected to a well terminal. Accordingly, capacitance is generated between the gate electrode and the N well of a varactor element. When the potential of the gate terminal is decreased, the two p+diffusion regions absorb positive holes serving as minority carriers from a channel region.

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