Voltage-controlled analog delay locked loop

Details Voltage-controlled analog delay locked loop Voltage-controlled analog delay locked loop

2006-07-04

2006-07-04

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S149000, C327S161000

Reexamination Certificate

active

07071745

ABSTRACT:
An analog delay locked loop for receiving a reference clock signal and for generating a delayed output clock signal includes a voltage controlled delay line, a fixed delay line, a delay voltage control, a fast/slow latch, a phase detector, as well as reset and clock off circuits. The fast/slow latch generates three signals that are received by the delay voltage control: a “latched slow signal”, a “latched fast signal”, as well as a “latched fast to slow signal”. The phase detector generates “go fast” and “go slow” signals that are received by the fast/slow latch. The analog delay locked loop sets the initial delay of the delay line at or near its minimum value on start-up. The delay is then forced to increase from the minimum value until a locking condition is achieved independent of the phase relationship between the reference and delayed clock signals.

REFERENCES:
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patent: 6339354 (2002-01-01), Heightley
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patent: 6359487 (2002-03-01), Heightley et al.
patent: 6469559 (2002-10-01), Heightley
patent: 6628154 (2003-09-01), Fiscus

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