Voltage control type delay circuit and internal clock generation

Details Voltage control type delay circuit and internal clock generation Voltage control type delay circuit and internal clock generation

1995-09-14

1998-03-24

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

327158, 327262, 327535, 327276, 331 57, H03K 514, H03L 100

Patent

active

057317275

ABSTRACT:
A control transistor is connected in parallel with an input transistor of a bias generation circuit in a voltage control delay circuit. A power supply potential Vcc is divided by voltage divider resistors to be applied to the gate of the control transistor. Reduction in the power supply potential Vcc causes reduction in a current Ib flowing to the control transistor, and a current Ic=Ia+Ib flowing to a delay time variable element. When the power supply potential Vcc is reduced, the factor of a delay time period of delay time variable elements becoming shorter due to a smaller amplitude of a clock signal is canceled with the factor of the delay time period of the delay time variable elements become longer due to a smaller current Ic flowing thereto. Therefore, variation in the delay time period can be suppressed to a low level.

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"6.255 Pull-in Range Digital PLL for ISDN Primary Rate Interface LSI" Kondoh et al., VLSI 1991; pp. 73-74.

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