Electricity: electrical systems and devices – Safety and protection of systems and devices – Load shunting by fault responsive means
Reexamination Certificate
2001-05-11
2003-12-16
Toatley, Jr., Gregory J. (Department: 2836)
Electricity: electrical systems and devices
Safety and protection of systems and devices
Load shunting by fault responsive means
C361S091100, C361S111000
Reexamination Certificate
active
06665160
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an electrostatic discharge (ESD) protection component, the relevant ESD Protection circuitry, and the ESD protection system.
2. Description of the Related Art
As the semiconductor manufacturing process develops, ESD protection has become one of the most critical reliability issues for integrated circuits (IC). In particular, as semiconductor process advances into the deep sub-micron stage, scaled-down devices, thinner gate oxides, lightly-doped drain regions (LDD), shallow trench isolation (STI) process and the metallic salicide process are more vulnerable in terms of ESD stress. Therefore, an efficient ESD protection circuit must be designed and placed on the I/O pad to clamp the overstress voltage across the gate oxide in the internal circuit.
FIG. 1A
shows a conventional ESD protection circuit where an N-type metal oxide semiconductor transistor (NMOS) NE is used as the primary ESD protection component and the gate of NE is connected to the source.
FIG. 1B
is the IV curve of the NMOS transistor in FIG.
1
A. Because NE is an enhanced-mode NMOS which is kept off under circuit operations, the external electronic signals can reach the internal circuit
12
via the I/O pad
10
. When a positive-ESD-pulse stress relative to VSS occurs at the I/O pad
10
, the drain voltage of the NE exceeds its trigger voltage V
trigger
(the breakdown voltage between the drain and the substrate of NE) which triggers the parasitic bipolar transistor (BJT) in NE. The ESD current should be released before any internal destruction caused by the ESD stress.
However, during the normal CMOS process, the breakdown voltage between the drain and source of the NMOS always climbs higher than 10v , possibly damaging the oxide gate produced in the CMOS process. Therefore, it is the main object for the ESD protection circuit to reduce the trigger voltage V
trigger
.
FIGS. 2A and 2D
are cross-sectional diagrams of the conventional NMOS. By ion implantation, a breakdown-trigger layer
20
or
22
is formed under the N+ diffusion of the drain and the source. The breakdown-trigger layer
20
or
22
is used to facilitate the breakdown of the PN-junction between the N+ diffusion
16
and the P-substrate
18
by lowering the breakdown voltage between the drain and substrate in the NMOS. Consequently, the timing for turning on the parasitic BJT in the NMOS is sped up to prevent damage to the internal circuits from the ESD stress.
Alternatively, SCR is adapted as the primary ESD protection component in the conventional ESD protection circuit. The SCR is off in the normal circuit operation state, but triggered to release the SD current during ESD stress. It is thus necessary to search for a suitable means of reducing the trigger voltage Vt when using SCR as the ESD protection component.
The object of the present invention is to lower the trigger voltage of ESD protection component.
Another object of the present invention is to provide an effective ESD protection to the connection pads in the IC.
SUMMARY OF THE INVENTION
An object of the present invention is to provide an electrostatic discharge (ESD) protection components applied on an integrated circuit (IC), and coup ed between a first and second connection pad. When a power supply is provided to the IC, the protection component is turned off, and when no power supply is provided, the protection component remains on to release ESD stress between the first connection pad and the second connection pad.
Another object of the present invention is to provide an LSD protection circuit for an IC, coupled to a first pad and a second pad. The ESD protection circuit comprises an ESD protection component and a bias generator. The ESD protection component is connected between the first pad and the second pad. The bias generator is used to turn off the ESD protection component when a power supply is provide to the IC. Conversely, when no power supply is provided to the IC, the ESD protection component is always on to release ESD stress between the first pad and the second pad.
The present invention further provides an ESD protection system for an IC. The IC comprises a plurality or connection pads, Pad
1
. . . PadN. The protection system comprises: an ESD bus line, a plurality of ESD protection component D
1
. . . DN and a bias generator. Each ESD protection Dn is connected between a correspondent Padn and the ESD bus line. The bias generator is used for providing a predetermined voltage to close D
1
. . . DN when a power supply is provided. D
1
. . . Dn is always on when no power supply is provided to release ESD stress between a Padx and a Pady.
The ESD protection component of the present invention can be either p-type or N-type depletion-mode metal oxide semiconductor transistor (MOS),
The advantage of the present invention is that through the ESD protection component of the present invention, the ESD current is easily dissipated. When there is no power supply provided to the IC, the ESD protection component is always on. Therefore, ESD stress is easily released through the ESD protection component of the present invention when no power supply is provided.
REFERENCES:
patent: 4385337 (1983-05-01), Asano et al.
patent: 5886862 (1999-03-01), Anderson et al.
patent: 6369998 (2002-04-01), Anderson
Ker Ming-Dou
Lin Geeng-Lih
Demakis James
Intellectual Property Solutions Incorporated
Toatley , Jr. Gregory J.
Vanguard International Semiconductor Corporation
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