Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion
Reexamination Certificate
1998-09-02
2001-10-16
Young, Brian (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Analog to digital conversion
C341S161000
Reexamination Certificate
active
06304206
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a voltage comparator, an operational amplifier, and an analog-to-digital conversion circuit, having an analog-to-digital converter and a multistage pipeline (multi-step flush) structure, employing the voltage comparator and the operational amplifier.
2. Description of the Prior Art
Following the recent development of the digital processing technique for video signals, an analog-to-digital conversion circuit (A-D converter) for processing video signals is increasingly demanded. In general, a two-step flush (two-step parallel) system is widely employed for such an analog-to-digital conversion circuit for processing video signals, which must perform high-speed conversion.
However, the analog-to-digital conversion circuit of the two-step flush system cannot attain sufficient conversion accuracy for an enormous number of converted bits. To this end, an analog-to-digital conversion circuit having a multistage pipeline (multi-step flush) structure has been developed.
FIG. 14
is a block diagram showing the structure of a conventional analog-to-digital conversion circuit
101
having a multistage pipeline structure. The analog-to-digital conversion circuit
101
shown in
FIG. 14
has a 10-bit four-stage pipeline structure.
Referring to
FIG. 14
, the analog-to-digital conversion circuit
101
includes a sample-and-hold circuit
102
, a first-stage circuit
103
, a second-stage circuit
104
, a third-stage circuit
105
, a fourth-stage circuit
106
, a plurality of latch circuits
107
and an output circuit
108
.
Each of the first-stage (initial stage) to third-stage circuits
103
to
105
comprises a sub A-D converter
109
, a D-A converter
110
and a differential amplifier
111
. The fourth-stage (final stage) circuit
106
comprises only a sub A-D converter
109
.
The first-stage circuit
103
has a 4-bit structure, and the second- to fourth-stage circuits
104
to
106
have 2-bit structures respectively.
Operations of the analog-to-digital conversion circuit
101
are now described. The sample-and-hold circuit
102
samples an analog input signal Vin and holds the same for a constant time. The analog input signal Vin outputted from the sample-and-hold circuit
102
is transferred to the first-stage circuit
103
.
In the first-stage circuit
103
, the sub A-D converter
109
A-D converts the analog input signal Vin. The sub A-D converter
109
transfers the result of A-D conversion, i.e., a high order 4-bit digital output (2
9
, 2
8
, 2
7
, 2
6
) to the D-A converter
110
while transferring the same to the output circuit
108
through four latch circuits
107
. The differential amplifier
111
amplifies the difference between the result of D-A conversion of the D-A converter
110
and the analog input signal Vin. The differential amplifier
111
transfers its output to the second-stage circuit
104
.
The second-stage circuit
104
performs operations similar to those of the first-stage circuit
103
on the output from the differential amplifier
111
of the first-stage circuit
103
. The third-stage circuit
105
performs operations similar to those of the first-stage circuit
103
on an output from the differential amplifier
111
of the second-stage circuit
104
. The second-stage circuit
104
provides an intermediate high order 2-bit digital output (2
5
, 2
4
), while the third-stage circuit
105
provides an intermediate low order 2-bit digital output (2
3
, 2
2
).
In the fourth-stage circuit
106
, the sub A-D converter
109
A-D converts an output from the differential amplifier
111
of the third-stage circuit
105
, to provide a low order 2-bit digital output (2
1
, 2
0
).
The digital outputs from the first- to fourth-stage circuits
103
to
106
simultaneously reach the output circuit
108
through the respective latch circuits
107
. In other words, the latch circuits
107
are adapted to synchronize the digital outputs from the circuits
103
to
106
with each other.
The output circuit
108
outputs a 10-bit digital output Dout of the analog input signal Vin in parallel after digital correction, if necessary.
Thus, in each of the first- to third-stage circuits
103
to
105
of the analog-to-digital conversion circuit
101
, the differential amplifier
111
amplifies the difference between the analog input signal Vin or the output from the differential amplifier
111
of the precedent circuit
103
or
104
and the result of D-A conversion of the digital output thereof.
Even if the number of converted bits is increased to reduce the least significant bit (LSB), therefore, the resolution of comparators forming each sub A-D converter
109
can be substantially improved for attaining sufficient conversion accuracy.
Following the recent speed increase of electronic apparatuses, a higher conversion speed is required to analog-to-digital converters. In order to increase the conversion speed of the aforementioned conventional analog-to-digital conversion circuit
101
, the GB product (gain-bandwidth product) of an operational amplifier forming each differential amplifier
111
must be increased. However, improvement of the GB product of the operational amplifier is limited. Therefore, it is difficult to further increase the conversion speed of the analog-to-digital conversion circuit
101
.
As hereinabove described, the A-D converter of each circuit is referred to as the sub A-D converter
109
, to be distinguished from the overall analog-to-digital conversion circuit
101
. A total parallel comparison (flush) system which can perform high-speed conversion is employed for the sub A-D converter
109
. The sub A-D converter
109
includes a plurality of comparators comparing an input voltage with a plurality of reference voltages. Each comparator is formed by a differential voltage comparator.
FIG. 15
is a circuit diagram of a conventional differential voltage comparator.
Referring to
FIG. 15
, a differential amplification circuit
10
includes P-channel MOS field-effect transistors (hereinafter referred to as PMOS transistors)
1
and
2
, N-channel MOS field-effect transistors (hereinafter referred to as NMOS transistors)
3
and
4
and a constant current source
7
.
The PMOS transistors
1
and
2
are connected between a node ND and output nodes NO
1
and NO
2
respectively. The NMOS transistors
3
and
4
are connected between the output nodes NO
1
and NO
2
and a node NS respectively.
The node ND is supplied with a power supply voltage V
DD
, while the node NS is grounded through the constant current source
7
. The PMOS transistors
1
and
2
are supplied with a bias voltage VB in the gates thereof respectively. The gates of the NMOS transistors
3
and
4
are connected to input nodes NA and NB respectively.
The input nodes NA and NB are connected to nodes N
1
and N
2
through capacitors
5
and
6
respectively. Switches SW
11
and SW
21
are connected between the input nodes NA and NB and the output nodes NO
1
and NO
2
respectively. Switches SW
12
and SW
13
are connected in parallel with the node N
1
, while switches SW
22
and SW
23
are connected in parallel with the node N
2
.
The switches SW
12
and SW
13
are supplied with input voltages V
1
(+) and V
2
(+) in input ends thereof respectively, while the switches SW
22
and SW
23
are supplied with input voltages V
1
(−) and V
2
(−) in input ends thereof respectively. Output voltages V
0
(+) and V
0
(−)are derived from the output nodes NO
1
and NO
2
respectively.
FIG. 16
is adapted to illustrate operations of the differential voltage comparator shown in FIG.
15
.
First, the switches SW
11
, SW
21
, SW
12
and SW
22
are moved to ON, while the switches SW
13
and SW
23
are moved to OFF. At this time, differential input voltages between the input nodes NA and NB and between the output nodes NO
1
and NO
2
are 0 V.
Then, the switches SW
11
and SW
21
are moved to OFF, and thereafter the switches SW
12
and SW
22
are moved to OFF, while the switches SW
13
and SW
23
are move
Tani Kuniyuki
Wada Atsushi
Armstrong Westerman Hattori McLeland & Naughton LLP
Nguyen John
Sanyo Electric Co,. Ltd.
Young Brian
LandOfFree
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