Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By amplitude
Reexamination Certificate
2001-01-26
2004-07-06
Nuton, My-Trang (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific signal discriminating without subsequent control
By amplitude
Reexamination Certificate
active
06759878
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
The subject application is related to subject matter disclosed in Japanese Patent Application No. H12-20810 filed on Jan. 28, 2000 in Japan to which the subject application claims priority under Paris Convention and which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a voltage comparator circuit in a CMOS integrated circuit. More specifically, the invention relates to a voltage comparator circuit for comparing voltages close to a ground or power supply potential, the voltage comparator circuit being used for detecting the occurrence of abnormality, such as a case where a p-n junction between the source and substrate of a CMOS integrated circuit is biased in a forward direction, in the control of a substrate potential.
2. Description of the Background Art
FIG. 7
shows a MOS differential amplifier circuit which is conventionally often used for comparing voltages.
The sources of a pair of N-channel MOS transistors (which will be hereinafter referred to as NMOS transistors) M
101
and M
102
are commonly connected to be grounded via a current source I
100
. The gate of the NMOS transistor M
101
is connected to an input terminal IN to which a signal V
IN
is inputted. The gate of the NMOS transistor M
102
is connected to an input terminal INN to which a signal V
INN
having the opposite phase to that of the input terminal IN is inputted. One end of a resistor R
101
is connected to the node a of the drain of the NMOS transistor M
101
, and the other end thereof is connected to a power supply VDD. One end of a resistor R
102
is connected to the node b of the drain of the NMOS transistor M
102
, and the other end thereof is connected to a power supply VDD. The node a is connected to the input terminal of a buffer S
1
to derive a signal from an output terminal OUT. In place of the signal V
INN
, a reference voltage Vref for comparing voltages may be applied to the input terminal INN.
The principle of operation of the differential amplifier circuit with this construction is well known as follows. The potential difference between the input terminals IN and INN causes a difference between the gate-to-source voltages V
GS
—
M101
and V
GS
—
M102
of the NMOS transistors M
101
and M
102
, to cause a difference between the proportions of currents of the NMOS transistors M
101
and M
102
, into which a current I
100
supplied from the current source I
100
is divided, i.e., a difference between a drain current I
D
—
M101
of the NMOS transistor M
101
and a drain current I
D
—
M102
of the NMOS transistor M
102
. These relationships are expressed as follows:
I
D
—
M101
=k
(
V
GS
—
M101
−Vth
)
2
(Expression 1)
I
D
—
M102
=k
(
V
GS
—
M102
−Vth
)
2
(Expression 2)
I
D
—
M101
+I
D
—
M102
=I
100
(Expression 3)
wherein Vth is the threshold voltage of the MOS transistor. The coefficient k is defined by the following expression using a gate width W, a gate length L, a gate capacity C
OX
and a mobility &mgr;
n
of electrons in Si.
K=
½&mgr;
n
C
OX
W/L
(Expression 4)
The drain currents I
D
—
M101
and I
D
—
M102
derived from the difference between the gate-to-source voltages V
GS
—
M101
and V
GS
—
M102
on the basis of the above described expressions are as follows.
I
D
—
M101
=I
100
/2
+k
(
V
GS
—
M101
−V
GS
—
M102
)/2{square root over ( )}{2
I
100
/k
−(
V
GS
—
M101
−V
GS
—
M102
)
2
} (Expression 5)
I
D
—
M102
=I
100
/2
−k
(
V
GS
—
M101
−V
GS
—
M102
)/2{square root over ( )}{2
I
100
/k
−(
V
GS
—
M101
−V
GS
—
M102
)
2
} (Expression 6)
A voltage is derived from the output terminal OUT via the buffer S
1
having a voltage Va of the node a which is generated by the current I
D
—
M101
flowing through the resistor R
101
. The voltage Va of the node a is expressed as follows.
Va=VDD−I
D
—
M101
R
101
(Expression 7)
This conventional circuit has a comparable voltage range of from about 0 V to a power supply voltage. If the reference potential Vref for comparing voltages is set to be 0 V or the power supply voltage to be used for comparing voltages approximating to the ground or power supply potential, there is a problem. If the reference potential Vref is set to be 0 V and if the voltage of the input terminal IN is set to be about 0 V, the source potentials of the NMOS transistors M
101
and M
102
become to negative potentials since the sources of the NMOS transistors M
101
and M
102
are connected to the ground potential via the current source. However, it is generally difficult to generate such negative potentials, if the reference potential Vref=0 V is applied to the input terminal INN, the gate-to-source voltage V
GS
—
M102
of the NMOS transistor M
102
is below the threshold voltage, so that the NMOS transistor M
102
is always turned off so as not to be operated. If the reference potential Vref is set to be the power supply potential and if the voltage of the input terminal IN is set to approximate to the power supply voltage, the source potentials of the NMOS transistors M
101
and M
102
increase. Therefore, there is a limit to the amplitude of the voltage Va of the node a which is the drain of the NMOS transistor M
101
, so that the buffer is difficult to receive signals.
Accordingly, if lower voltages than the ground potential are compared with each other, a differential amplifier circuit shown in
FIG. 8
has been conventionally used. A level shifter circuit is added for converting voltages which are applied to the gates of NMOS transistors M
111
and M
112
. One end of a resistor R
121
is connected to an input terminal IN, and the other end thereof is connected to a constant current source I
121
and the gate of the NMOS transistor M
111
. One end of a resistor R
122
is connected to an input terminal INN, and the other end thereof is connected to a constant current source I
122
and the gate of the NMOS transistor M
112
. By always passing currents I
121
and I
122
through the resistors R
121
and R
122
, the voltages of the other ends of the resistors R
121
and R
122
are shifted by a predetermined voltage with respect to the input terminals IN and INN. Thus, even if lower voltages than the ground potential are compared with each other, the gate potentials of the NMOS transistors M
111
and M
112
can be in the range of from about 0 V to the power supply voltage, which is a voltage range capable of being compared by conventional circuits. However, in this method, there are problems in that current consumption increases since the currents I
121
and I
122
must be passed through the level shifter circuit and that the currents I
121
and I
122
are passed through the input terminals. In the case of a voltage comparator circuit for use in the detection of a substrate potential, it is desired to prevent such currents from passing through the input terminals into the substrate. Because the burden imposed on a substrate bias generating circuit is increased by the currents, which thus flow into the substrate, to increase current consumption.
There is also considered a method for changing the ground potential, to which the current source I
100
of the differential amplifier circuit shown in
FIG. 7
is connected, into a negative potential to increase the range of comparable input voltages. However, in this method, there is a problem in that it is required to additionally provide a power supply voltage.
A simple circuit shown in
FIG. 9
is also known. The source of an NMOS transistor M
130
is connected to the ground potential, the drain thereof is connected to one end of a resistor R
130
and the input terminal of a buffer S
1
, and the gate thereof is connected to an input terminal IN. The other end of the resistor R
130
is connected to a power supply potential VDD, and the output terminal of the buffer S
1
is connected to an o
Kabushiki Kaisha Toshiba
Nuton My-Trang
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
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