Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Amplitude control
Reexamination Certificate
2000-06-22
2001-08-28
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Amplitude control
C327S180000, C327S318000, C361S091200, C361S111000
Reexamination Certificate
active
06281735
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to voltage clamping circuits for limiting the voltage range of a signal which would otherwise exceed predetermined maximum and minimum signal peaks, and in particular, to voltage clamping circuits that provide asymmetrical, or unipolar, voltage clamping.
2. Description of the Related Art
As integrated circuits become increasingly complex and the number of functions they perform become more numerous, it becomes increasingly important that such integrated circuits be capable of interfacing with signal sources that generate large or otherwise unusual signals. This is particularly true in mixed signal applications where the integrated circuit is often a digital circuit that operates with binary logic and is powered by a low voltage power supply and yet must be capable of dealing with analog signals which can exceed the voltage or current handling capabilities of the integrated circuit.
For example, integrated circuits for controlling video monitors that use cathode ray tubes (CRTs), such as those typically used with personal computers, must be able to work with many types of large signals. One example would be the horizontal and vertical flyback pulses generated during the horizontal and vertical retrace intervals, respectively, of the video display. Referring to
FIG. 1
, in the case of the horizontal flyback pulses, such pulses can be in the range of 100 volts peak-to-peak, with much of the signal being positive but also some of the signal being negative with respect to the system reference, or ground.
Referring to
FIG. 2
, the integrated circuit that must deal with such high magnitude signal pulses will have an internal amplifier stage A
1
which is responsible for converting such pulses into a digital pulse stream. An external resister Rext will be used to limit the input current to the integrated circuit to a predetermined maximum positive value during the flyback interval and a predetermined negative value during the normal forward scan interval. Typically, diodes D
1
, D
2
are also used at the input terminal to provide protection against electrostatic discharge (ESD) events in accordance with well-known techniques. The digital pulses HBLANK are for use elsewhere in the system for things such as blanking the video signal within the video amplifier and synchronizing a phase lock loop used in an on-screen display (OSD) generator.
Referring to
FIG. 3
, it is desirable that the digital output pulse HBLANK should trigger to its high signal state before the rising edge of the flyback pulse has passed through the zero volt level (time interval t1). Similarly, it is desirable that it then trigger to its low signal state soon after falling below the zero volt level (time interval t2).
Since the integrated circuits used in such an application are typically powered by a signal-ended power supply, such as a positive five volt power supply, it is important that the negative signal excursions of the input flyback signal HFLYBACK somehow be prevented from affecting the input terminal of the integrated circuit. As is well know, such negative signal excursions can cause current to flow within the substrate of the integrated circuit due to a reverse current flow at the input terminal. Accordingly, it would be desirable to have some form of voltage clamping circuit which provides asymmetrical, or unipolar, clamping of the input signal to prevent a negative voltage from appearing at the input terminal notwithstanding any negative voltage excursions of the input signal. (The term unipolar as used herein in intended to mean those signals having peak values within the range of zero to a positive voltage, inclusive, or zero to a negative voltage, inclusive.)
SUMMARY OF THE INVENTION
An input signal voltage clamping circuit in accordance with the present invention provides asymmetrical, or unipolar, voltage clamping for an input signal terminal of a circuit. For a circuit having a positive power supply voltage relative to its ground, or reference, terminal and an input signal having positive and negative signal peaks, the input signal terminal voltage is clamped at positive and zero voltage levels. The input signal terminal voltage is clamped at a positive clamp voltage level which is intermediate to the power supply and ground potentials when the input signal voltage is greater than such positive clamp voltage. The input signal terminal voltage is clamped at a zero volt level when the input signal voltage is negative.
An input signal voltage clamping circuit in accordance with one embodiment of the present invention includes first and second power terminals, an input signal terminal, first and second input clamping circuits and a bias circuit. The first and second power terminals are for conveying a power supply voltage with the second power terminal having a power supply voltage magnitude and polarity relative to the first power terminal;. The input signal terminal is for conveying an input signal having an input signal magnitude with opposing peak signal magnitude values that have positive and negative polarities relative to the first power terminal. The first input clamping circuit, coupled between the input signal terminal and the first power terminal, clamps the input signal terminal at a first clamped voltage in response to reception of the input signal, wherein: the first clamped voltage has a nonzero magnitude which is less than the power supply voltage magnitude and a same polarity as the power supply voltage relative to the first power terminal; and the received input signal has magnitude values which are greater than the first clamped voltage and a same polarity as the first clamped voltage relative to the first power terminal. The bias circuit, coupled to at least one of the first and second power terminals, provides a bias signal in response to reception of a bias current. The second input clamping circuit, coupled between the bias circuit, the input signal terminal and the second power terminal, clamps the input signal terminal at a second clamped voltage in response to reception of the bias signal and reception of the input signal, wherein: the second clamped voltage is substantially zero relative to the first power terminal; and the received input signal has magnitude values which are nonzero and an opposite polarity as the first clamped voltage relative to the first power terminal.
A method for clamping an input signal voltage of a circuit in accordance with another embodiment of the present invention includes the steps of:
receiving a power supply voltage via first and second power terminals with the second power terminal having a power supply voltage magnitude and polarity relative to the first power terminal;
receiving, via an input signal terminal, an input signal having an input signal magnitude with opposing peak signal magnitude values that have positive and negative polarities relative to the first power terminal;
clamping the input signal terminal at a first clamped voltage in response to reception of the input signal, wherein
the first clamped voltage has a nonzero magnitude which is less than the power supply voltage magnitude and a same polarity as the power supply voltage relative to the first power terminal, and
the received input signal has magnitude values which are greater than the first clamped voltage and a same polarity as the first clamped voltage relative to the first power terminal;
generating a bias signal; and
clamping the input signal terminal at a second clamped voltage in response to reception of the bias signal and reception of the input signal, wherein
the second clamped voltage is substantially zero relative to the first power terminal, and
the received input signal has magnitude values which are nonzero and an opposite polarity as the first clamped voltage relative to the first power terminal.
REFERENCES:
patent: 4989057 (1991-01-01), Lu
patent: 5528910 (1996-06-01), Honningford
patent: 5530612 (1996-06-01), Maloney
patent: 5610790 (1997-03-01), Staab et al.
pat
Callahan Timothy P.
Dalla Valle Mark A.
National Semiconductor Corporation
Nguyen Hai L.
Wildman, Harrold, Alle & Dixon
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