Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Amplitude control
Reexamination Certificate
2002-07-09
2003-09-02
Lam, Tuan T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Amplitude control
C330S009000
Reexamination Certificate
active
06614280
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to linear integrated circuits, and more particularly to low-dropout (LDO) voltage regulators implemented in CMOS.
2. Description of the Related Art
In the design of a low-dropout (LDO) regulator, which can typically operate with only a 100 mV drop over the output MOS transistor, and also in every linear output stage of an operational amplifier (OPAMP) etc. there is a strong demand for a low-ohmic control of the large gate of the output transistor. This is necessary in order to push the gate pole to high frequencies and to keep the feedback system stable. Often this is done by using an emitter follower. In the standard n-well CMOS technology one can use the pnp transistor formed by the p+ Source/Drain implant (emitter), n-well (base) and p-substrate (collector). With the decreasing feature size of the CMOS technology the current gain (beta) of this bipolar transistor becomes smaller and smaller because of shallower emitters. In a typical 0.7 um technology the beta is about 50 but in a typical 0.35 um technology the beta is only about 5. So the emitter follower does not have any longer an effect.
The common approach for a rail-to-rail buffer would be to use two differential input pairs; one NMOS-input for voltages from V
dd
to about N-V
th
(threshold voltage of an NMOS), and one PMOS-input for voltages from V
ss
to about N-V
th
. Then it is necessary to control the gate voltage from V
dd
to V
ss
. This approach has a lot of drawbacks. It is quite complex, it needs a double current in the input pairs and there might be the need for a gm-control (transconductance) of the input pairs to keep the buffer stable for all input voltages.
U.S. Patents which relate to LDO devices are:
U.S. Pat. No. 6,225,857 (Brokaw) teaches a driver circuit for an LDO pass device. The circuit is capable of low output impedance, such that when driving a high gate capacitance of a MOS device the resulting pole is moved to a higher frequency than would be otherwise possible.
U.S. Pat. No. 6,188,211 (Rincon-Mora et al.) discloses an LDO voltage regulator circuit comprising MOS and bipolar transistors and a feedback network coupled to an error amplifier.
U.S. Pat. No. 6,046,577 (Rincon-Mora et al.) describes an LDO having a rail-to-rail buffer circuit and incorporates a transient response boost circuit requiring no standby or quiescent current during zero output current load conditions.
Because the above-cited examples of the related art do not satisfy the requirements of the circuit designer to drive a large output gate, a new approach is required. One way is the use of a voltage buffer made by an operational transconductance amplifier (OTA) or an operational amplifier (OPAMP). This buffer must fulfill the following requirements:
rail-to-rail in/output operation, i.e. it must be able to drive the gate from below the threshold voltage (V
th
), i.e., off-state, to the supply rail, i.e., on-state,
high current efficiency, i.e., it should have not more current consumption than an
emitter follower,
small silicon area,
no extra poles,
stable with high capacitive loads and high bandwidth.
The present invention fulfills these requirements.
SUMMARY OF THE INVENTION
It is an object of at least one embodiment of the present invention to provide circuits and a method for a voltage buffer-with nearly rail-to-rail in/output operation, i.e., it is able to drive the gate from about threshold voltage (V
th
) to the supply rail.
It is another object of the present invention to provide high current efficiency.
It is yet another object of the present invention to minimize the size of the silicon real estate required over the related art.
It is still another object of the present invention to avoid extra voltage buffer poles.
It is a further object of the present invention is to provide a circuit which is stable with high capacitive loads and has a high bandwidth by pushing the gate pole to high frequencies to make the feedback loop stable.
It is yet a further object of the present invention is to provide a circuit which uses standard CMOS devices only.
It is still a further object of the present invention is to reduce power consumption to an absolute minimum.
These and many other objects have been achieved by utilizing a single mismatched input transistor pair which provides systematic offset and operates in the weak inversion mode. With a systematic offset in the input transistor pair the buffer is able to bring the gate voltage of the output MOS transistor to values below V
dd-V
th
which makes the output MOS transistor nonconductive. Since there is still a sufficient current flow in the buffer it still controls the gate low-ohmic. The biasing of the input transistor pair is controlled by a dynamic biasing circuit as follows. With a low output current the current source for the dynamic biasing circuit is in the linear region and its bias current for the buffer input is near zero. With a high current output the current source is in saturation and the full additional current flows in the buffer input. The current level in the buffer is, therefore, high. Because a separate well is used in the standard CMOS N-well technology the backgate effect (body effect) can be exploited to provide a lower threshold voltage (V
th
) through biasing of the common bulk (body/substrate). The common bulk of the dynamic biasing circuit and of the input transistor pair are coupled via a resistive means providing a voltage drop of typically 350 mV. The common bulk of the input transistor pair is therefore biased at V
dd
-350 mV to reduce the threshold voltage of the input transistor pair. However, when the buffer input voltage is near zero Volt the input pair may come into the linear region and it is desirable to have the highest possible V
th
. This is done by placing a circuit between the common bulks of the dynamic biasing circuit and the input transistor pair which shorts out the resistive means and restores the well potential to V
dd
. A MOS transistor will typically provide this function. Because there will be no current flow in the buffer when the input voltage goes to V
dd
an additional current source is coupled to the output of the buffer to keep the output at V
dd
. The feedback is made stable by allowing a high gain in it.
REFERENCES:
patent: 4429234 (1984-01-01), Streit
patent: 4563597 (1986-01-01), Betzold
patent: 5726597 (1998-03-01), Petty et al.
patent: 6046577 (2000-04-01), Rincon-Mora et al.
patent: 6072349 (2000-06-01), Pippin et al.
patent: 6124704 (2000-09-01), Annema
patent: 6140872 (2000-10-01), McEldowney
patent: 6157259 (2000-12-01), Dasgupta
patent: 6188211 (2001-02-01), Rincon-Mora et al.
patent: 6225857 (2001-05-01), Brokaw
patent: 6275094 (2001-08-01), Cranford et al.
patent: 6388521 (2002-05-01), Henry
patent: 6400225 (2002-06-01), Kruiskamp
Ackerman Stephen B.
Dialog Semiconductor GmbH
Lam Tuan T.
Saile George O.
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