Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
1999-06-09
2001-05-01
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C327S537000
Reexamination Certificate
active
06225854
ABSTRACT:
BACKGROUND OF THE INVENTION
This application claims priority from Korean patent application No. 98-21235 filed Jun. 9, 1998 in the name of Samsung Electronics Co., Ltd., which is incorporated by reference.
1. Field of the Invention
The present invention relates generally to voltage boosting circuits, and more particularly, to power supply voltage boosting circuits having cross-coupled precharge circuits.
2. Description of the Related Art
Signals in dynamic random access memories (DRAMs) constructed using CMOS transistor technology experience a voltage drop of somewhat more than the threshold voltage of a MOS transistor while being transmitted through the channel region of the MOS transistor. Such voltage drops can cause information loss and interfere with data read and write operations.
Continuous increases in the density and capacity of semiconductor memory devices have caused a commensurate increase of power consumption. Therefore, semiconductor memory devices use internal power supply voltages to reduce power consumption and enhance reliability.
To correctly read and write data from or to a memory cell composed of a MOS transistor and a capacitor, a voltage sufficient to overcome the threshold voltage of the MOS transistor must be provided. For example, the internal power supply voltage is typically boosted by 1.5V to drive word lines that are connected to the gates of the MOS transistors.
FIG. 1
is a block diagram of a conventional power supply voltage boosting circuit, and
FIG. 2
is a circuit diagram showing more details of the circuit of FIG.
1
.
Referring to
FIG. 1
, the power supply voltage boosting circuit shown generally at
1
generates a boosted voltage Vpp which is higher than a power supply voltage (for example the internal power supply voltage Vcc) and includes a detector
12
, oscillator
14
, first and second drivers
16
and
22
, first and second pumping circuits
18
and
24
(also referred to as main pumping circuits), and first and second precharge circuits
20
and
26
.
Detector
12
, which detects whether the voltage Vpp is higher than a predetermined target voltage level, is coupled to a power line
10
which transfers the voltage Vpp to other circuits. Detector
12
generates a signal DET which goes low to disable the oscillator
14
when Vpp is higher than the target level. When Vpp is lower than the target level, detector
12
drives the signal DET to a logic high level to enable the oscillator. As shown in
FIG. 2
, detector
12
includes to resistors R
1
and R
2
coupled in series between the power line
10
and a power supply ground terminal. An inverter INV
11
has in input terminal connected to the node between R
1
and R
2
and an output terminal for generating the signal DET.
Referring again to
FIG. 1
, oscillator
14
generates an oscillation signal OSC which is enabled or disabled in response to the detection signal DET. When DET is high, the oscillator
14
outputs the oscillation signal OSC which oscillates with a predetermined period. When DET is low, the oscillation signal OSC is disabled and remains, for example, at a logic high level. As shown in
FIG. 2
, oscillator
14
includes a 2-input NAND gate G
1
and two series connected inverters INV
2
and INV
3
. Refening again to
FIG. 1
, the first driver
16
, the first pumping circuit
18
and the first precharge circuit
20
form a first boosted voltage generating section which performs a pumping operation to raise the potential of power line
10
during a first half period of the oscillation signal OSC. As shown in
FIG. 2
, the first driver
16
includes
3
series connected inverters INV
6
, INV
7
and INV
8
, which receive the oscillating signal OSC and output a first signal &phgr;1.
The first pumping circuit
18
includes a pumping capacitor C
2
and two NMOS transistors M
3
and M
4
. Transistor M
3
is diode-connected between Vcc and a pumping node N
2
, and M
4
is diode-connected between node N
2
and the power line
10
. Capacitor C
2
is connected between the output of the first driver
16
and the gate of M
4
at node N
2
. The first precharge circuit
20
includes two inverters INV
4
and INV
5
, a pumping capacitor C
1
, and two NMOS transistors M
1
and M
2
. Inverters INV
4
and INV
5
are connected in series to generate a second signal &phgr;2 in response to OSC. Transistor M
1
is diode-connected between Vcc and a pumping node N
1
, while M
2
is diode-connected between nodes N
1
and N
2
. Capacitor C
1
is connected between the gate of M
2
at node N
1
and the output of INV
5
to receive the signal &phgr;2.
Referring back to
FIG. 1
, the second driver
22
, the second pumping circuit
24
, and the second precharge circuit
26
form a second boosted voltage generating section which performs a pumping operation to raise the potential of power line
10
during a second half period of the oscillation signal OSC. As shown in
FIG. 2
, the constituent components of the second boosted voltage generating section are essentially identical to those of the first section, with pumping nodes N
3
and N
4
corresponding to pumping nodes N
1
and N
2
, respectively, and signals &phgr;2B and &phgr;1B corresponding to signals &phgr;1 and &phgr;2, respectively. However, the second precharge circuit
26
and the second driver
22
are driven by a second oscillating signal OSCB which is complement of OSC and is obtained through inverter INV
9
. Because the two sections operate during alternate half cycles of the oscillation signal OSC, two pumping operations are performed during each cycle of OSC.
The operation of the power supply voltage boosting circuit
1
will now be described more thoroughly with reference to
FIGS. 1 and 2
.
When the oscillation signal OSC switches from a high to a logic low level, capacitor C
1
in the first precharge circuit
20
performs a negative pumping operation so that node N
1
is charged to a voltage of VCC-Vtn via the transistor M
1
(where Vtn represents a threshold voltage of an N-type MOS transistor). Since the output signal &phgr;1 from the first driver
16
switches to a logic high level, node N
2
in the first pumping circuit
18
is boosted to 2VCC-Vtn via capacitor C
2
.
At the same time, since the output signal &phgr;1B from the second driver
22
switches to a logic low level, capacitor C
4
in the second pumping circuit
24
performs a negative pumping operation so that node N
4
is charged to a voltage of VCC-Vtn via the NMOS transistor M
7
. Node N
3
in the second precharge circuit
26
is boosted to 2VCC-Vtn by the capacitor C
3
, so that node N
4
is then precharged to a voltage of 2VCC-2Vtn. Hereinafter, the above described operation is referred to as “a precharge pumping operation”.
When the oscillation signal OSC switches from a low to a logic high level, the power line
10
is boosted to 3VCC-3Vtn by the second pumping circuit
24
, and node N
2
is precharged to a voltage of 2VCC-2Vtn through the first precharge circuit
20
.
More specifically, at the low-to-high transition of OSC, the signal &phgr;1B from the second driver
22
goes high, so node N
4
is boosted to 3VCC-2Vth via capacitor C
4
. Therefore, the power line
10
is boosted to 3VCC-3Vtn through NMOS transistor M
8
(hereinafter, the above described operation is referred to as “a main pumping operation”). Capacitor C
3
performs a negative pumping operation, so node N
3
is charged to a voltage of VCC-Vtn. At the same time, capacitor C
2
in the first pumping circuit
18
performs a negative pumping operation because the signal &phgr;1 from the first driver
16
switches to a logic low level. Capacitor C
1
pumps node N
1
in the first precharge circuit
20
to a voltage of 2VCC-Vtn in response to the signal &phgr;2 from the invertor INV
5
so that node N
4
is precharged to a voltage of 2VCC-2Vtn. That is, the precharge pumping operation is performed.
As described above, at the low-to-high transition of the oscillation signal OSC, the precharge pumping operation for node N
2
is performed while the second pumping circuit
24
performs the main pumping opera
Cunningham Terry D.
Marger & Johnson & McCollom, P.C.
Samsung Electronics Co,. Ltd
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