Voltage boosting circuit having asymmetric MOS in DRAM

Details Voltage boosting circuit having asymmetric MOS in DRAM Voltage boosting circuit having asymmetric MOS in DRAM

1999-05-17

2000-10-10

Cunningham, Terry D.

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

327390, G05F 110, G05F 302

Patent

active

061305731

ABSTRACT:
A voltage boosting circuit having an asymmetric MOS in DRAM. A gate of a first NMOS connects to a voltage source, and a source region of the first NMOS connects to a row decoder. A gate of the asymmetric NMOS connects to a drain region of the first NMOS. A drain region of the asymmetric NMOS connects to a column decoder, and a source region of the first asymmetric NMOS connects to a word line. A gate of a second NMOS connects to the column decoder, a source region of the second NMOS connects to a ground terminal and a drain region of the second NMOS connects to a source region of the first asymmetric NMOS.

REFERENCES:
patent: 4805152 (1989-02-01), Kogan
patent: 5783962 (1998-07-01), Rieger

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