Voltage boosting circuit and operating method thereof

Details Voltage boosting circuit and operating method thereof Voltage boosting circuit and operating method thereof

1989-12-21

1991-04-23

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307578, 307443, 307450, 307451, H03K 458, H03K 19017, H03K 1704, H03K 19094

Patent

active

050102591

ABSTRACT:
An input signal is inverted by a CMOS inverter and provided for an output signal line. The CMOS inverter is provided between a power supply and a ground, and its node on the side of the power supply is charged all the time to prevent the potential thereof from being lowered. An output signal provided for the output signal line is delayed by a delay circuit to be applied to a boosting capacitor. The potential of the node is further boosted by this boosting capacitor. Consequently, the potential of the output signal is also boosted. When the potential of the node is raised higher than a supply voltage, an N channel MOSFET for charging is turned off to prevent a reverse flow of a charge.

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Makoto Taniguchi et al, "Fully Boosted 64K Dynamic RAM with Automatic and Self-Refresh," IEEE Journal of Solid-State Circuits, vol. SC-16, No. 5, Oct. 1981, pp. 492-498.

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