Voltage boosting circuit

Details Voltage boosting circuit Voltage boosting circuit

1999-06-30

2000-11-14

Nelms, David

Static information storage and retrieval

Powering

36518909, 365102, G11C 700

Patent

active

061479233

ABSTRACT:
An NMOS capacitor 13 and a PMOS capacitor 18 for pumping up are connected in series to an output line 12. In middle point voltage control circuit 20, a power supply line at VCC is connected via a PMOS transistor 21 to the anode of a reverse-flow preventing diode 22 and the node of voltage VM, the cathode of the diode 22 is connected via an NMOS transistor 23 to a ground line, and control signals *BIN and AIN are provided to the gate electrodes of the transistors 21 and 23, respectively, in response to an address transition detection signal AT. An end point voltage control circuit 30 is connected between the gate electrode of the NMOS transistor 23 and one end of the PMOS capacitor 18, and is equipped with inverters 31 and 32 connected in series. In an initial state, VM is at 0V and VE and VOUT is at VCC. Next the node of VM becomes a floating state and VE is lowered to 0V. Finally the node of VM is raised to VCC to boost VOUT from VCC up to VCC(2+.alpha.), where 0<.alpha.<1.

REFERENCES:
patent: 3646369 (1972-02-01), Fujimoto
patent: 4639622 (1987-01-01), Goodwin et al.
patent: 5751158 (1998-05-01), Loughmiller
patent: 5781426 (1998-07-01), Matsushita
patent: 5877650 (1999-03-01), Matsushita

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