Miscellaneous active electrical nonlinear devices – circuits – and – Gating – Signal transmission integrity or spurious noise override
Reexamination Certificate
2003-03-27
2004-02-17
Nguyen, Long (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Gating
Signal transmission integrity or spurious noise override
C327S536000, C363S060000
Reexamination Certificate
active
06693480
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to CMOS integrated circuits, and more particularly to voltage booster circuits.
Bus switches manufactured with semiconductor technology are used for high-speed network routing and switching applications. Complementary metal-oxide-semiconductor (CMOS) transistors may be used for bus switches, but using just an n-channel transistor without a parallel p-channel transistor reduces gate capacitance. The bus switch can connect or isolate two networks attached to the sources and drains of the transistors.
A bus-switch resistance of only 4 to 6 ohms between the networks is desirable. One solution is to boost the gate voltage to the n-channel transistor that acts as a bus switch. The gate voltage can be boosted above the power supply by a voltage-booster circuit. For example, the gate voltage can be boosted to 4.3 volts using a capacitive pump with a 3-volt power supply. See for example, U.S. Pat. No. 5,946,204 by Wong et al., assigned Pericom Semiconductor Corp. of San Jose, Calif.
Sequence of Events During Boosting FIG.
1
FIG. 1
is a diagram of a sequence of events when boosting the gate voltage above Vcc for the circuit of FIG.
2
. The input signal disables the pull-down of the boosted node, step
31
. Rather than generate a pulse, the boosted node (V_BOOST) is driven to Vcc, step
32
.
A Schmidt-trigger inverter senses when the boosted node reaches Vcc, or a voltage slightly below Vcc, step
33
. After a delay through a delay line, step
34
, the gate of the transistor pulling V_PULSE up to Vcc is then disabled, step
37
. The delay line also drives the back-side of the capacitor from ground to Vcc, step
38
. This voltage swing is capacitivly coupled through the capacitor to the boosted node, step
40
. The voltage on the boosted node is boosted up to about Vpp, depending on the capacitive coupling ratio.
A small keeper pull-up is enabled, step
36
. This keeper device is not large enough to pull the boosted node to the charge-pump voltage Vpp, but is large enough to compensate for small leakage currents from the boosted node.
This sequence of events first drives the boosted gate node to Vcc, and then after a delay the boosted node is driven to Vpp by capacitive coupling. Enabling and disabling of keeper and pull-down devices are precisely coordinated to maximize the voltage boost.
Voltage Booster Circuit FIG.
2
FIG. 2
is a schematic diagram of a prior-art voltage booster. When V_IN is high, the boosted node (V_BOOST) is grounded so bus-switch transistor
26
is turned off. The back-side node (V_BACK_CAP) is also grounded, so that both sides of capacitor
24
are grounded. Transistors
55
,
56
, and
58
are off, disabling all pull-up current paths. The boosted node is pulled down to ground by pull-down n-channel transistor
48
when V_IN is high.
P-channel transistor
55
is a non-series-connected pull-up used to initially drive the boosted node to Vcc. The gate of p-channel transistor
55
, V_PULSE, is initially high but is driven low through n-channel transistors
95
,
96
when the input V_IN goes low. Inverter
90
drives high the gate of n-channel transistor
96
while n-channel transistor
95
is already on since it is driven high by Schmidt-trigger inverter
91
which senses the initial low voltage on V_BOOST.
Once p-channel transistor
55
drives V_BOOST to near Vcc, Schmidt-trigger inverter
91
switches its output low, disabling n-channel transistor
95
. Inverter
92
turns on n-channel pullup transistor
97
, which pulls V_PULSE up to Vcc-Vtn. Then inverter
93
enables p-channel transistor
94
to drive V_PULSE all the way up to Vpp, completely shutting off p-channel transistor
55
.
Charge pump
60
drives the sources to Vpp of a p-channel pull-up transistor within inverter
88
in the delay line. The delay line has its input connected to the boosted node by Schmidt-trigger inverter
91
, and includes inverters
92
,
93
driving p-channel transistor
94
and inverter
76
that drives the back-side of capacitor
24
from ground to Vcc after the delay through the delay line. Inverters
76
,
92
,
93
and Schmidt-trigger inverter
91
are not connected to Vpp to reduce current drawn from Vpp. Thus only part of the delay line, inverter
88
, is charge-pumped.
P-channel transistors
56
,
58
act as small keeper transistors to compensate for any leakage currents in the boosted node. The source and N-well terminals of p-channel keeper transistor
56
are connected to Vpp from charge pump
60
. The N-well substrates of transistors
55
,
58
are connected to Vpp so that the p+-to-substrate diodes at the sources of these transistors do not become forward biased and conduct current from the boosted node.
P-channel transistors turn on when their gates are at least a p-channel threshold below their sources. If Vpp is more than a threshold above Vcc, and is applied to the source of transistors
56
, then the transistor could turn on when the gate is driven to Vcc when it should be off. Sub-threshold currents can also be a problem even if the gate-to-source voltage is somewhat less than a threshold. To avoid these problems, the gate of transistor
56
is driven high to Vpp rather than to Vcc, so that the gate-to-source voltage is zero when the transistor is intended to be off. Inverter
88
in the delay line are thus connected to Vpp rather than Vcc so that it drives the gates of transistor
56
high to Vpp. The substrates of transistors
94
,
55
are also connected to Vpp.
Capacitor
24
is constructed from a p-channel transistor with its source, drain, and substrate (bulk) terminals connected together as the back-side node of capacitor
24
, while the transistor's gate is the front-side node, the boosted node. Using the gate of capacitor
24
for the boosted node reduces leakage and parasitic capacitances. A p-channel transistor is used to construct capacitor
24
so that it can have its own N-well; n-channel transistors share a common p-type substrate.
While such a voltage-booster circuit is useful for driving the gate of a bus-switch transistor, reduced power supplies have reduced the boost provided by such a circuit. Since the voltage boost is to about double Vcc, when Vcc is reduced, the absolute voltage boosted to is also reduced. It is therefore desirable to provide a larger voltage boost. A boost circuit that can boost to a larger multiple of the Vcc power supply is desirable for low-voltage applications.
REFERENCES:
patent: 3639696 (1972-02-01), Chambers et al.
patent: 5361237 (1994-11-01), Chishiki
patent: 5412604 (1995-05-01), Fukuda et al.
patent: 5592115 (1997-01-01), Kassapian
patent: 5675279 (1997-10-01), Fujimoto et al.
patent: 5847946 (1998-12-01), Wong
patent: 5889427 (1999-03-01), Nakajima
patent: 5946204 (1999-08-01), Wong
patent: 5982224 (1999-11-01), Chung et al.
patent: 6069828 (2000-05-01), Kaneko et al.
patent: 6127875 (2000-10-01), Allen et al.
patent: 6157225 (2000-12-01), Micheloni et al.
patent: 6157242 (2000-12-01), Fukui
Auvinen Stuart T.
Nguyen Long
Pericom Semiconductor Corp.
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