Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
1999-10-20
2002-08-13
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C327S537000, C307S110000, C363S060000
Reexamination Certificate
active
06433623
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a voltage booster circuit; and, in particular, the invention relates to a voltage booster (step-up) circuit which is suitable for boosting a power supply in an integrated semiconductor circuit packaged in an integrated circuit, such as a microprocessor and the like, which requires a voltage having a wide operating range.
Recently, for a microprocessor, a demand for low voltage operation and low power consumption has been increasing in order to meet the demand to mount the microprocessor into a portable machine. Namely, in the case of a microprocessor that is normally comprised of CMOS logic circuits, if a power supply voltage which exceeds a threshold voltage Vth of its MOS transistor is available, the logic operation of each CMOS gate which constitutes its logic circuits is ensured, although the operation speed thereof may drop somewhat. If, however, its power supply voltage drops, for example, from 5 volts to below 2 volts, because a voltage across the gate and the source of the MOS transistor approaches the threshold voltage Vth of MOS transistor, the on-resistance of the MOS transistor increases. In particular, in a circuit that uses a transfer gate, in a MOS transistor which constitutes the transfer gate, voltage across the gate and the source may drop below Vth according to the terminal voltage that the transfer gate transfers. In such a case, the on-resistance of its transfer gate becomes extremely great, thereby preventing transfer of a normal voltage level. Further, in a memory module, such as a mask ROM or the like, a drop in the power supply voltage means a drop in a word line drive voltage in a memory mat. Namely, it means that among a plurality of memory MOS transistors constituting the memory mat, for those memory MOS transistors whose gate is connected to the word lines, a voltage across the gate and the source thereof drops to cause a drain current of the memory MOS transistor to attenuate, thereby resulting in an increase in data read time.
Therefore, in order to cope with a case having a specification of a low power supply voltage, for example, below 2 V, a desired operation is ensured even under a low power supply voltage by adoption of a method as described, for example, in JPA Laid-Open No. 8-149801, whereby its low power supply voltage is boosted for driving its transfer gate (MOS side gate) and memory module word lines.
SUMMARY OF THE INVENTION
In the related art described above, a technique is adopted wherein, in principle, a stepped-up voltage, corresponding to twice the power supply voltage VCC which is applied to a power supply terminal, is constantly produced in a boost cycle, including a charging period and a charge transfer period; and, wherein, more specifically, a first terminal of a booster capacitance, which is charged to a level of the power supply voltage VCC, is further charged by applying the power supply voltage via a switching circuit in the charging period thereof, and in the charge transfer period after the charging period, the charge having been accumulated in the booster capacitance is transferred to a load via an output terminal. Therefore, if an integrated semiconductor circuit device having a conventional built-in booster circuit is used as a power supply voltage VCC, which has a relatively high voltage region, for example, 4 V or more, a resulting step-up voltage produced by the booster circuit may exceed a withstand voltage of the device (MOS transistor), thereby deteriorating reliability of the system and/or causing breakdown of the devices. However, if a clamp circuit (which is comprised of three PMOS transistors connected in series, and a threshold voltage of each PMOS transistor is set at Vthp) is connected in parallel between the first terminal of the booster capacitance and the terminal of the power supply, namely in parallel with the switching circuit, the booster circuit can be clamped at a voltage of power supply voltage VCC plus 3 times |Vthp|.
Nowadays, however, withstand voltages of the devices are on the decrease along with the trend for devices having finer patterns, and, therefore, an upper limit in the range of power supply voltage VCC and an allowable application voltage (or withstand voltage of the device) are coming into close proximity. Therefore, in the aforementioned voltage clamping method, on the side of the upper limit in the range of power supply voltage VCC, there is a concern that the clamp voltage may exceed its allowable application voltage.
On the other hand, in order to lower the clamp voltage, a voltage drop in the voltage clamp circuit may be minimized, for example, by reducing the number of series connections of PMOS transistors that constitute the voltage clamp circuit. However, this method, if applied to a case having a specification of the power supply voltage VCC in a low voltage range, in contrast to the above, the boost efficiency thereof drops, so that the clamp voltage cannot be reduced simply. Further, as for the clamp voltage, because a fluctuation as great as an integer times the number of connections, i.e., three times in the case of three series connections, results in a condition relative to a fluctuation of a device parameter, i.e., Vthp, of each of the PMOS transistors that constitute its voltage clamp circuit, attainment of compatibility between the low voltage range and the high voltage range for ensuring a high boost efficiency in the low voltage range, while limiting the boost voltage in the high voltage range, is difficult. Still further, because there exists a certain time lag until the voltage clamp is enabled after the voltage clamp circuit is operated, there may arise a peak voltage in excess of its clamp voltage due to that time lag.
Further, as a method for preventing the occurrence of an over-voltage, a depletion type NMOS transistor (hereinafter referred to as a D-MOS) may also be connected between the power supply and the power supply terminal, as disclosed in the aforementioned JPA, so as to clamp the voltage itself to be applied to the power supply terminal. If this method is adopted, in a range of power supply voltage VCC above a threshold voltage |VthD| of the D-MOS, because the voltage of the power supply terminal can be clamped at a level of |VthD|, a boost voltage can certainly be suppressed to approximately twice of |VthD|.
In contrast, however, in a case where the power supply voltage VCC drops below |VthD| a boost voltage twice as great as the power supply voltage VCC is produced. Therefore, if a D-MOS is used, a boost voltage of 2 times |VthD| must exist in a voltage range that has as its low limit voltage a voltage used by a circuit, and as an upper limit voltage, an allowable application voltage. In addition, in consideration of the fluctuation in device parameters as described above, it becomes more difficult to suppress the boost voltage within a predetermined voltage range with a drop in the upper limit of the allowable application voltage. Still further, use of a D-MOS causes increases in the number of mask sheets and processes in the manufacture of semiconductor chips, thereby increasing the cost of manufacture disadvantageously. For example, even when a D-MOS is used in circuits other than the booster circuit mounted on the same chip as their components, unless each D-MOS thereof is operable at the same threshold voltage as the booster circuit device, additional masks and/or additional processes will be required eventually.
An object of the present invention is to provide for a booster circuit apparatus that can regulate a level of voltage boosting according to the magnitude of its power supply voltage.
In order to accomplish the above-mentioned object of the invention, a booster circuit is provided by a method which is comprised of the steps of: applying a power supply voltage to one terminal of a booster capacitance interposed between a power supply terminal and an output terminal in a charging period
Okutsu Mitsuhiko
Sato Shoji
Callahan Timothy P.
Englund Terry L.
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