Voltage boost reset circuit for a flash memory

Details Voltage boost reset circuit for a flash memory Voltage boost reset circuit for a flash memory

2000-02-09

2001-06-05

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Powering

C365S230060, C365S189110

Reexamination Certificate

active

06243316

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates generally to semiconductor memory devices. More particularly, the present invention relates to an improved boost reset circuit for a flash memory.
In the design of integrated circuits, there is a trend to power the integrated circuits using decreasing supply voltage levels. Previous circuit families operated at 5 volts and 3.3 volts. Current families operate at 1.8 volts and future families will operate at 1.0 volts nominal supply voltage. These lower supply voltages create design and operation problems.
One design problem relates to accessing a core cell of the memory device. The voltage swing available in a 1.0 volt supply system is typically insufficient for a read or a program of a flash memory cell. Accordingly, boost circuits have been developed to provide the necessary voltage variation. For accessing the core cell, a word line voltage is boosted to, for example, 4.0 volts. This allows the core cell transistor to fully turn on and the core cell to sink enough current for rapid sensing of the state of the cell.
To control operation of the boost circuit, particularly when many address inputs are changing, a reset circuit is incorporated in the boost circuit. The reset circuit responds to address transitions by resetting the boosted voltage to a reset value. However, the reduction in supply voltage for the memory to 1.0 volts. interferes with the operation of the reset circuit. A p-channel transistor used for resetting the boosted voltage cannot be adequately turned on at low supply voltage to ensure rapid reset.
Accordingly, an improved reset circuit for a boost circuit for a memory device is required for operation at reduced supply voltages.
SUMMARY
By way of introduction only, an improved voltage boost reset circuit includes a zero-threshold transistor coupled to the boosted node. The voltage of the boosted node is boosted to a predetermined voltage by the boost circuit for increasing memory word line voltages. To improve the performance and response time of the boosted node, the reset circuit applies a voltage to turn on the zero-threshold transistor very strongly. Accordingly, the boosted node is rapidly reset for subsequent boosting. When boosting is occurring, the zero-threshold transistor is turned off to isolate a reset voltage from the boosted voltage.
The foregoing discussion of the preferred embodiments has been provided only by way of introduction. Nothing in this section should be taken as a limitation on the following claims, which define the scope of the invention.


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patent: 5642313 (1997-06-01), Ferris
patent: 5696731 (1997-12-01), Miyamoto
patent: 6002630 (1999-12-01), Chuang et al.
patent: 6078531 (2000-06-01), Miyazima et al.
patent: 6134146 (2000-10-01), Bill et al.

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