Voltage boost circuit with low power supply voltage

Details Voltage boost circuit with low power supply voltage Voltage boost circuit with low power supply voltage

2000-06-26

2002-03-12

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Gating

Signal transmission integrity or spurious noise override

C327S536000

Reexamination Certificate

active

06356137

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates in general to integrated circuits, and in particular to a voltage boost circuit that provides efficient voltage boosting for circuits operating at lower power supply voltages.
Certain integrated circuit applications require internally generating a secondary voltage source that is often larger in magnitude than the primary externally supplied power source. For example, some non-volatile memory circuits, such as electrically erasable programmable read only memories (EEPROMs), that may use a single power supply voltage of, for example, 3.5 volts, also require a programming or erase voltage that is much larger in magnitude (e.g., 12 volts). Voltage multiplying or charge pump techniques have been developed to internally generate the higher voltage from the primary supply voltage. Charge pump circuits take advantage of charge storing capability of capacitors to, for example, double the level of a primary supply voltage by bootstrapping. A typical charge pump circuit may include transistors that transfer charge to one or more capacitors in response to an oscillating (or clock) signal. In some implementations, the charge pump circuit requires non-overlapping clock signals whose voltage levels are themselves boosted to higher than power supply level. The higher the boosted level of the clock signal, the faster the charge pump can give rise to the target output voltage level.
One known circuit implementation for generating boosted clock signals for charge pumps is shown in FIG.
1
. The signal at the output node, OUT, is discharged to ground by n-channel transistor Q
1
when VDIS is high. When VDIS goes low, transistor Q
1
turns off and p-channel transistor Q
3
turns on. A depletion mode (negative Vt) transistor Q
2
operates to isolate OUT from transistor Q
3
. During the first half of the clock cycle, signal VPCH turns on transistor Q
2
allowing OUT to get precharged up to the power supply voltage Vcc. During the second half of the clock cycle a boost signal VBT is applied to one terminal of pump capacitor Cp raising the voltage level at OUT from Vcc up toward twice Vcc. The negative threshold voltage of depletion transistor Q
2
allows output voltage OUT to swing above the precharge voltage. The operation of this circuit is illustrated by the timing diagram of FIG.
2
.
There are a number of drawbacks with this type of boosting circuit. First, the process must provide for a depletion mode transistor, which is not readily available in conventional CMOS fabrication processes. Second, the efficiency of the circuit is reduced by the fact that pumping occurs only during a portion of the clock half-cycle, as opposed to the entire half-cycle. Current leakage through the depletion transistor further reduces the circuit efficiency, where the output voltage can get close to but not quite double the power supply voltage. This effect is further exacerbated at lower power supply voltages where it becomes increasingly difficult to fully turn off the depletion transistor. At lower power supply voltages, therefore, this circuit becomes ineffective and ultimately non-functional.
There is a need for a voltage boosting circuit that operates efficiently at lower power supply voltages.
SUMMARY OF THE INVENTION
The present invention provides method and circuitry for efficiently boosting voltage for low power supply applications. In a specific embodiment, the present invention provides a phase boosting circuit that boosts a clock signal to substantially twice the power supply voltage level in a single half-cycle. The circuit eliminates the need for a depletion transistor and can thus be implemented using conventional complementary metal-oxide-semiconductor (CMOS) fabrication processes. A novel voltage summing circuit allows the phase doubler of the present invention to achieve greater boosting capability for applications with ultra low power supply voltages.
Accordingly, in one embodiment, the present invention provides a voltage boosting circuit having an input that receives an input signal and an output that generates a boosted output signal, the circuit including a pull-down transistor coupled between the output of the circuit and a low potential and having an input coupled to the input of the circuit; a charge transfer transistor coupled between a precharge node and the output of the circuit and having an input coupled to the input of the circuit; a precharge transistor coupled between a power supply and the precharge node and having an input coupled to the output of the circuit; a capacitive element having a first terminal coupled to the precharge node; and an inverter having an input coupled to the input of the circuit and an output coupled to a second terminal of the capacitive element.
In another embodiment, the present invention provides a low power voltage boosting circuit the includes two voltage boosting circuits as described in the preceding paragraph, whose outputs are capacitively summed by a third boost circuit, wherein the third boost circuit includes a pull-down transistor, a charge transfer transistor and a precharge transistor coupled as described above.
A better understanding of the nature and advantages of the voltage boosting circuit according to the present invention will be gained with reference to the detailed description below and the accompanying drawings.


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