Voltage adjusting circuit

Details Voltage adjusting circuit Voltage adjusting circuit

2000-07-25

2001-07-24

Han, Jessica (Department: 2838)

Electricity: power supply or regulation systems

Self-regulating

Using a three or more terminal semiconductive device as the...

C323S314000

Reexamination Certificate

active

06265858

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a voltage adjusting circuit, and in particular, to a voltage adjusting circuit capable of stabilizing a voltage used as a cell plate voltage and a bit line precharge voltage for a dynamic random access memory (DRAM).
2. Background of the Related Art
In the related art, a half VCC voltage is used as a cell plate voltage V
CP
for a capacitor electrode to determine a quantity of electric charge of a signal, or as a bit line precharge voltage V
BLP
to determine a standard of signal detection. Accordingly, a half VCC generating circuit must rapidly respond to variations of a power supply voltage VCC and a load to maintain precision of the half VCC voltage.
FIG. 1
illustrates a block diagram of a related art half VCC generating circuit
100
that generates the bit line precharge voltage V
BLP
and the cell plate voltage V
CP
in accordance with a bit line precharge signal BLP.
FIG. 2
illustrates a first example of the related art half VCC generating circuit
100
consisting of first and second resistors R
1
, R
2
and having an output voltage Vout represented by:
Vout=(R
1
/(R
1
+R
2
))*VCC.  (1)
When the first resistor R
1
and the second resistor R
2
have substantially equal resistances, the power supply voltage VCC is divided equally by the first and second resistors R
1
, R
2
. Thus, the output voltage Vout becomes a half VCC voltage. The first example of the related art half VCC generating circuit
100
includes only the first and second resistors R
1
, R
2
, and is thus quite simple.
However, the first related art example has various disadvantages. For example, the related art first example circuit consumes much current.
FIG. 3
illustrates a second example of the related art half VCC generating circuit
100
, having a bias circuit
10
that reduces current consumption and a push-pull output circuit
11
that enhances a driving force. The bias circuit
10
includes first and second transistors QN
1
, QP
1
and first and second resistors R
1
, R
2
. The first transistor QN
1
is of a diode NMOS type, and has a first electrode and a control electrode commonly connected to the first resistor R
1
at a first node N
1
. The first transistor QN
1
has a second electrode commonly connected to a first electrode and a control electrode of the second transistor QP
1
at a second node N
2
, wherein the second transistor is of a diode PMOS type. A second electrode and the control electrode of the second transistor QP
1
are commonly connected to the second resistor R
2
at a third node N
3
. The first resistor R
1
is connected between the first node N
1
and the power supply voltage VCC, and the second resistor R
2
is connected between the third node N
3
and the ground VSS.
The push-pull circuit
11
includes a third NMOS transistor QN
2
and a fourth PMOS transistor QP
2
. The third transistor QN
2
has a first electrode connected to the power supply voltage VCC, a control electrode connected to the first node N
1
, and a second electrode commonly connected to the output voltage Vout and a first electrode of the fourth transistor QP
2
. The fourth transistor QP
2
also has a control electrode connected to the third node N
3
and a second electrode connected to the ground VSS.
If the resistances of the first and second resistors R
1
, R
2
are sufficiently large in the bias circuit
10
, a voltage of the second node N
2
becomes the half VCC voltage, as described above. When threshold voltages of the first through fourth transistors QN
1
, QP
1
, QN
2
, QP
2
are equally set at Vt, voltages of the first and third nodes N
1
, N
3
are equal to (VCC/2)+Vt and (VCC/2)−Vt, respectively. As a result, a stable half VCC voltage is generated as the output voltage Vout. A gate-source voltage V
GS
of the third and fourth transistors QN
2
, QP
2
in the push-pull output circuit
11
is also set at Vt, and thus, the third transistor QN
2
and the fourth transistor QP
2
are at a state just before being fully transited to the “ON” position, and a through current flows therein.
Accordingly, when the output voltage Vout is varied from the half VCC voltage, one of the third and fourth transistors QN
2
, QP
2
is transited to the “ON” position, and the other is fully transited to the “OFF” position, to rapidly restrict variation of the half VCC voltage. Since N-well bias voltages of the second and fourth transistors QP
1
, QP
2
are a half VCC voltage and a full VCC voltage, respectively, the fourth transistor QP
2
receives more back gate effects than the second transistor QP
1
, and thus, a threshold voltage Vtp
2
of the fourth transistor QP
2
becomes greater than a threshold voltage Vtp
1
of the second transistor QP
1
. As a result, when the output voltage Vout maintains a half VCC level, the second transistor QP
2
is always transited to the “ON” position, and thus the through current does not flow in the push-pull output circuit
11
.
Even if the third transistor QN
2
and the fourth transistor QP
2
are sufficiently increased in size to have a large load capacity, the consumption of power at the push-pull output circuit
11
is not increased. In addition, the current flowing in the bias circuit
10
can be reduced by increasing the values of the first and second resistors R
1
, R
2
.
However, the related art half VCC generating circuit has various problems and disadvantages. The cell plate voltage V
CP
depends on the VCC voltage, especially at a low voltage. Thus, the transient property of the related art circuit can result in various problems. For example, an absolute value difference of the threshold voltages of the NMOS type transistor and the PMOS the transistor becomes a setting error of the half VCC voltage generating circuit. When the NMOS transistor and PMOS transistor each have a process error of ±0.1V, respectively, the absolute value of the error of the half VCC voltage generating circuit equals 0.2V. Further, if the external power supply voltage is decreased, the relative error increases.
In addition, when a capacitance of the cell plate electrode or the bit line is increased four times in accordance with a generation of a dynamic random access memory DRAM, the driving capacity of the half VCC voltage generating circuit does not improve significantly, thereby worsening a transient response property of the half VCC generating circuit. A significant amount of time is thus required to obtain the stable half VCC voltage when the power supply voltage is applied. Furthermore, the half VCC generating circuit cannot rapidly respond to a sharp variation of the load or a VCC variation during operation of the DRAM.
FIG. 4
graphically illustrates a variation of the half VCC voltage according to the load variation in an active mode and a standby mode that results in various problems and disadvantages. The half voltage outputted from the half VCC voltage generating circuit
100
maintains a constant level at an initial operation, but decreases due to the current consumption in the active mode, including a read/write operation and a sense amp operation. If the half VCC voltage becomes lower than &Dgr;V, a defect may occur in a cell data.
Additionally, the half VCC voltage cannot maintain a predetermined level and causes voltage bouncing when the standby mode (i.e., a refresh operation) has a load. This phenomenon often takes place during an auto refresh operation, thus influencing the DRAM operation.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a voltage adjusting circuit that stably maintains a voltage, regardless of variations of an external voltage and a load.
It is another object of the present invention to provide a voltage adjusting circuit that can respond rapidly to a sharp variation in the load or VCC during operation, and improve a transient response property of the voltage adjusting circuit.
In order to achieve the above-described object of the present invention, there is provided a voltage adjuster circuit including a

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