Semiconductor device manufacturing: process – With measuring or testing
Reexamination Certificate
2005-11-15
2005-11-15
Wilczewski, Mary (Department: 2822)
Semiconductor device manufacturing: process
With measuring or testing
C438S637000, C438S638000, C438S666000, C438S672000, C438S687000
Reexamination Certificate
active
06964874
ABSTRACT:
The invention provides a technique of monitoring the void formation in a damascene interconnection process. According to the invention, a test structure is provided that includes at least two damascene structures that have at least one different cross-sectional geometric parameter. To monitor the void formation, the test structure is cut to expose a cross-sectional view to the damascene structures. The cross-sectional view is then inspected and the void formation is investigated in each of the damascene structures. The invention is particularly applicable to multi-level copper-based dual-damascene interconnection processes to monitor the voiding at the interface between barrier layers and bottom metal trenches. The invention allows monitoring of the void formation by locating only one structure on the chip and performing only one cut.
REFERENCES:
patent: 5821168 (1998-10-01), Jain
patent: 6103539 (2000-08-01), Schaffer et al.
patent: 6252227 (2001-06-01), Tseng et al.
patent: 6253621 (2001-07-01), Jarvis
patent: 6294396 (2001-09-01), Nogami et al.
patent: 6351516 (2002-02-01), Mazor et al.
patent: 6498384 (2002-12-01), Marathe
patent: 2002/0125905 (2002-09-01), Borden et al.
patent: 2002/0168786 (2002-11-01), Langer et al.
patent: 2004/0026693 (2004-02-01), McLaughlin et al.
patent: 2005/0112788 (2005-05-01), Borden et al.
patent: WO01/80304 (2001-10-01), None
Kelvin, Y. Y. et al., “Stress-Induced Voiding and Its Geometry Dependency Characterization,” IEEE 41st Annual International Reliability Physics Symposium 2003, pp. 156-160.
Lin, M. H. et al., “Comparison of Copper Interconnect Electromigration Behaviors in Various Structures for Advanced BEOL Technology,” IEEE Proceedings of 11th IPFA 2004, pp. 177-180.
Park, Byung-Lyul et al., “Mechanisms of Stress-Induced Voids in Multi-Level Cu Interconnects,” Proceedings of the IEEE 2002 International Interconnect Technology Conference, Jun. 3-5, 2002 pp. 130-132.
Reid et al., “Optimization of Damascene Feature Fill for Copper Electroplating Process,” IEEE International Conference Interconnect Technology 1999, May 24-26, 1999 pp. 284-286.
Oshima et al., “Improvement of Thermal Stability of Via Resistance in Dual Damascene Copper Interconnection,” International Electron Devices Meeting, 2000. IEDM Technical Digest, Dec. 10-13, 2000 pp. 123-126.
Hu et al., “Bimodal Electromigration Mechanisms in Dual-Damascene Cu Line/Via on W,” Proceedings of the IEEE 2002 International Interconnect Technology Conference, 2002. Jun. 3-5, 2002 pp. 133-135.
Guldi et al., “Characterization of Copper Voids in Dual Damascene Processes,” Advanced Semiconductor Manufacturing 2002 IEEE/SEMI Conference and Workshop, Apr. 30-May 2, 2002 pp. 351-355.
Gill et al., “Investigation of Via-Dominated Multi-Modal Electromigration Failure Distrubutions in Dual Damascene Cu Interconnects with a Discussion of the Statistical Implications,” 40th Annual Reliability Physics Symposium Proceedings, Apr., 2002.
Sakata et al., “Solid Phase Replacement Process for Multilevel High-Aspect Ration Al Fill Applications,” Proceedings of the IEEE 1998 International Interconnect Technology Conference, 1998. Jun. 1-3, 1998 pges 81-83.
Yoshida et al., “Stress-Induced Voiding Phenomena for an Actual CMOS LSI Interconnects,” International Electron Devices Meeting, 2002. IEDM '02 Digest, Dec. 8-11, 2002 pp. 753-756.
Gan et al., “Contrasting Failure Characteristics of Different Levels of Cu Dual-Damascene Metallization,” Proceedings of the International Symposium on the Physical and Failure Analysis of Integrateed Circuits, 2002. Jul. 8-12, 2002 pp. 124-128.
von Glascow, A. et al., “New Approaches for the Assessment of Stress-Induced Voiding in Cu Interconnects,” Proceedings of the IEEE 2002 International Interconnect Technology Conference, 2002. Jun. 3-5, 2002 pp. 274-276.
Ogawa et al., “Stress Induced Voiding Under Vias Conneected to Wide Cu metal Leads,” 40th Annual Reliability Physics Symposium Proceedings, 2002. Apr. 7-11, 2002 pp. 312-321.
Lu et al., “Understanding and Eliminating Defects in Electroplated Cu Films,” Proceedings of the IEEE 2001 Interconnect Technology Conference, 2001. Jun. 4-6, 2001 pp. 280-282.
Ogawa et al., “Statistics of Electromigration Early Failures in Cu/Oxide Dual-Damascene Interconnects,”IEEE 01CH37167, 39thAnnual International Reliability Physics Symposium, Orlando, Florida (2001).
Motte et al., “Damascene Test Structures for the Evaluation of Barrier Layer Performance Against Copper Diffusion,”Microelectronic Engineering55:291-296 (2001).
Filippi et al., “Electromigration in AlCu Lines: Comparison of Dual Damascene and Metal Reactive Ion Etching,”Thin Solid Films388:303-314 (2001).
Berger et al., “Electromigration Characterization Versus Texture Analysis in Damascene Copper Interconnects,”Mat. Res. Soc. Symp. Proc. 612:D2.4.1-D2.4.6 (2000).
Hübler Peter
Koschinsky Frank
Werner Thomas
Advanced Micro Devices , Inc.
Thomas Toniae M.
Wilczewski Mary
Williams Morgan & Amerson P.C.
LandOfFree
Void formation monitoring in a damascene process does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Void formation monitoring in a damascene process, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Void formation monitoring in a damascene process will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3503900