Voiceband data set circuitry with dual bus architecture

Details Voiceband data set circuitry with dual bus architecture Voiceband data set circuitry with dual bus architecture

1980-09-08

1983-06-14

Zache, Raulfe B.

Boots, shoes, and leggings

375 8, G06F 100

Patent

active

043886973

ABSTRACT:
A full duplex, synchronous data set (10) includes primary signal processing circuitry which generates a modulated transmit data signal in response to serial data from a terminal interface (17). The modulated data signal is transmitted over a primary channel of a transmit line (11). The primary signal processing circuitry also receives modulated data signals from a primary channel of a receive line (12) and recovers therefrom a serial bit stream for presentation to the interface. The operating parameters of the primary signal processing circuitry are specified by a primary controller (30) over a plurality of buses (PA, PC, PD). The primary controller includes a microprocessor (310) and associated peripherals (315, 320, 325, 330, 335). Encoder (115) and decoder (175) circuits within the primary signal processing circuitry are each comprised of a plurality of modules (1310, 1340, 1440, 1460, 1510, 1710, 1835, 1840, 1960, 1980) each designed to perform a specific function. The modules are operated in a selected sequence, with signals passing from one module to the next via a local bus (LEB, LDB).

REFERENCES:
patent: 4035777 (1977-07-01), Moreton
patent: 4159882 (1979-07-01), Sanders, Jr. et al.
Sherman et al., "System Description of a Programmable Multiple Data Set," Proc. 1975 Nat. Tele Conf., pp. 23-9 to 23-12.
Tanabe et al., "16-Bit Microprocessor With Dual Bus Architecture for Multi-Microprocessor System," Proc. 1979 Spring Compcon, pp. 98-101.
MacSorley, "Processor to Processor Final Communications," IBM T.D.B., vol. 22, No. 2, pp. 656-658, Jul. 1979.

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