Pulse or digital communications – Pulse code modulation – Differential
Patent
1994-09-28
1996-09-17
Chin, Stephen
Pulse or digital communications
Pulse code modulation
Differential
341 77, 341143, H03M 732
Patent
active
055576354
ABSTRACT:
The encode and decode subsystems use a continuously variable slope delta-modulation (CVSD) approach, with either parallel or serial data transfers. To allow for synchronization with a stable data transfer, the entire subsystem uses the main acquisition systems bit rate clock (BRC) as a basis. All other clocks required are simply divided down versions of the BRC and a request pulse from the main system to transfer the data. The delta-modulator is clocked at a rate commensurate with the word placement in the minor frame of the data acquisition cycle; the NRZ-L bits are clocked into serial-to-parallel registers, then latched into the parallel discrete interface (PDI) unit of the main data system. For a serial feed, a similar situation is possible by clocking the data off the circuit board into a serial discrete interface (SDI) unit. The request pulse that activates, the transfer is synchronized with the BRC to ensure a stable transfer. The decoder uses the same CVSD integrated circuit to decode the digital data. The decoder is able to lock onto the data stream as a parasitic extension of a standard PCM decommutator. To locate the data and establish the necessary clocking, the standard word rate clock (WRC), frame rate clock (FRC), and the BRC of the decommutators are used.
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Daniel T. Laird, Pragmatic Design, Design Test Expo, Jan. 12-14, 1993, pp. 1-4.
Chin Stephen
Franz Bernard E.
Kundert Thomas L.
May Timothy J.
The United States of America as represented by the Secretary of
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