VMOS transistor and method of fabrication

Details VMOS transistor and method of fabrication VMOS transistor and method of fabrication

1978-08-09

1980-05-06

Tupman, W. C.

Metal working

Method of mechanical manufacture

Assembling or joining

29578, 29580, B01J 1700

Patent

active

042009685

ABSTRACT:
A vertical insulated gate field effect transistor having a first first conductivity layer, a second second conductivity layer thereon, a third first conductivity layer thereon, a groove extending from the surface of the third layer through the second layer into the first layer, a layer of insulation and gate material in the groove and a shallow first conductivity vertical region extending from the third layer into the second layer along the groove to form a short channel in the second layer with a shallow device junction.
The device is fabricated by masking the three semiconductor layers and etching the third layer and part of the second layer to form a groove, diffusing second conductivity impurities to a shallow depth in the groove, continue the etching to extend the groove through the second layer into the first layer. A layer of insulation and gate material are formed in the groove to produce the vertical channel.

REFERENCES:
patent: 3975221 (1976-08-01), Rodgers
patent: 4003126 (1977-01-01), Holmes
patent: 4056413 (1977-11-01), Yoshimura
patent: 4105475 (1978-08-01), Jenne

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