VMOS Read only memory

Details VMOS Read only memory VMOS Read only memory

1978-03-20

1980-04-15

Fears, Terrell W.

Static information storage and retrieval

Read only systems

Semiconductive

365 51, 365178, 29571, G11C 1140

Patent

active

041986938

ABSTRACT:
A VMOS read only memory or ROM array is formed by a process compatible with standard N-channel silicon gate manufacturing methods used for circuitry peripheral to the array. The ROM array is programmed after the top level of contacts and interconnections, usually metal, has been deposited and patterned for the periphery. Each cell is formed with a very short channel in a V-shaped anisotropically etched groove. Address lines and gates are polysilicon, and the output lines are defined by elongated N+ regions. The ground or Vss connection to the source of each transistor in the array is provided by a buried N+ epitaxial layer. Each potential MOS transistor in the array is programmed to be a logic "1" or "0" by ion implanting through the polysilicon gates and thin gate oxide, using patterned protective oxide as a mask, or using photoresist as a mask prior to application of protective oxide.

REFERENCES:
patent: 4059826 (1977-11-01), Rogers

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