VMOS Floating gate memory with breakdown voltage lowering region

Details VMOS Floating gate memory with breakdown voltage lowering region VMOS Floating gate memory with breakdown voltage lowering region

1978-05-30

1980-09-09

Larkins, William D.

Static information storage and retrieval

Magnetic bubbles

Guide structure

357 23, 357 55, 357 59, 357 60, 357 89, 365185, H01L 2710, G11C 1140

Patent

active

042220637

ABSTRACT:
A semiconductor electrically programmable read only memory device (EPROM) utilizes an array of memory cells each in the form of a single V-type MOSFET which achieves the normal AND function (Data-Word Address) using a capacitance coupled version of threshold logic. Each MOSFET is formed by a V-shaped recess at the intersection of each bit line and word line that extends across the diffused bit line, (which serves as the transistor drain) and into the substrate (which serves as the source and ground plane of the device). A similarly V-shaped floating gate is isolated below and above the crossing bit and word lines by thin oxide layers. A ring of P-type conductive material around the upper end of each V-shaped recess and adjacent its surrounding N-type drain region serves to lower the required programming voltage without increasing the device threshold voltage.

REFERENCES:
patent: 3868187 (1975-02-01), Masuoka
patent: 4016588 (1977-04-01), Ohya et al.
Rodgers et al., VMOS Memory Technology, IEEE Journal of Solid-State Circuits, vol. SC-12, No. 5, Oct. 1977, pp. 515-524.
Jenne' et al., "VMOS EPROM and Buried Source RAM Structures", IEDM Late News Papers, (Suppl. to 1976 IEDM Technical Digest), pub. Dec. 5, 1976.

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