VMOS Floating gate memory device

Details VMOS Floating gate memory device VMOS Floating gate memory device

1976-05-04

1980-09-09

Larkins, William D.

Static information storage and retrieval

Magnetic bubbles

Guide structure

357 23, 357 55, 357 59, 357 60, 357 71, 365185, H01L 2710, G11C 1140

Patent

active

042220629

ABSTRACT:
A semiconductor programmable read only memory device (PROM) utilizes an array of memory cells each having an area basically defined by the intersection of a bit line and a word address line. On a substrate of one conductivity type is an upper layer of material of the opposite conductivity within which are diffused bit lines of the same conductivity material as the substrate. The crossing address lines are conductive material formed on an insulating layer that covers the diffused bit lines and the upper layer. Each cell is a single transistor element in the form of a V-type MOSFET which achieves the normal AND function (Data-Word Address) using a capacitance coupled version of threshold logic. Each MOSFET is formed by a V-shaped recess at the intersection of each bit line and address line that extends through the diffused bit line, (which serves as the transistor drain) and into the substrate (which serves as the source and ground plane of the device). A similarly V-shaped floating gate is isolated below and above the crossing bit and address lines by thin oxide layers. Data is written into the cell when hot electrons are injected into the gate oxide near the drain junction and attracted to the floating gate which has been charged positive by capacitance coupling from the word line. The hot electrons are generated from the channel current via impact ionization at the pinched-off drain junction.

REFERENCES:
patent: 3825945 (1974-07-01), Masuoka
patent: 3975221 (1976-08-01), Rogers
patent: 3992701 (1976-11-01), Abbas et al.
Rogers et al., "VMOS: . . . ", IEEE J. of Solid-State Circuits, vol. SC9, No. 5, Oct. 1974, pp. 247-249.

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