1996-08-27
2000-01-11
Teska, Kevin J.
G01R 3102
Patent
active
060145048
ABSTRACT:
Fault simulation apparatus 10 that simulates faults in a piece of equipment 12 coupled to a VME bus 11. A computer 30 generates user defined faults that are to be simulated and provides initialization data and control signals to VME fault insertion apparatus 20 coupled between the VME bus 11 and the piece of equipment 12. The VME fault insertion apparatus 20 comprises bus fault logic 15 interposed in request and acknowledgment signal lines and data lines, that intercepts normal bus data transmission, and inserts user-defined data into bus data that is transmitted to the equipment 12 to simulate failures therein in response to fault definition signals 23. A fault processor 16 receives initialization data and control signals from the computer 30, sets an address of the VME fault insertion apparatus 20, interprets received commands, outputs address select signals that decode the address lines, and outputs fault definition signals 23 to the bus fault logic 15 in response to the initialization data and control signals that define the fault that is to be simulated. Function select logic 13 decodes the address lines in response to the address select signals provided by the fault processor 16 that enables selected data paths through the bus fault logic 15. Using the present invention, a user can easily activate and deactivate simulated faults in the equipment 12. Failures are activated and deactivated at the computer via an easy-to-use computer interface.
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patent: 5204864 (1993-04-01), Won
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patent: 5633813 (1997-05-01), Srinivan
Held Gerald E.
Norris David A.
Saine David C.
Do Thuan
Lenzen, Jr. Glenn H.
Raytheon Company
Schubert William C.
Teska Kevin J.
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