VLSI Wired-OR driver/receiver circuit

Details VLSI Wired-OR driver/receiver circuit VLSI Wired-OR driver/receiver circuit

1982-03-08

1985-02-19

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

375 36, H03K 1700

Patent

active

045009880

ABSTRACT:
Bidirectional communication upon a high performance synchronous (25 MHz line transfer rate) parallel digital communication bus interconnecting large numbers (up to 256 along 1 meter of bus) of very large scale integrated (VLSI) cirucit devices is supported by VLSI wired-Or driver/receiver (D/R) circuit elements synergistically operative under a two-time-phase bus electrical protocol for bus drive. During a first phase of approximately 10 nanoseconds all interfacing driver circuits additively drive, or pull-up, connected bus lines to a +3 v.d.c. logical High condition. During a second phase of approximately 20 nanoseconds during each 40 nanosecond cycle time D/R circuits present high impedance to charged bus lines for maintenance of such logical High and transmission of a logical "0", or else one or more D/R circuits drain line charge toward 0 v.d.c. for transmission for a logical "1". Two point driver to receiver, wired-OR, broadcast, and/or eavesdrop communication are supported for bus lines.

REFERENCES:
patent: 4024501 (1977-05-01), Herring et al.
patent: 4101734 (1978-07-01), Dao
patent: 4216389 (1980-08-01), Carter
patent: 4337465 (1982-06-01), Spracklen et al.
patent: 4388725 (1983-06-01), Saito et al.

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