VLSI triple-diffused polysilicon bipolar transistor structure

Details VLSI triple-diffused polysilicon bipolar transistor structure VLSI triple-diffused polysilicon bipolar transistor structure

1990-01-08

1991-10-29

Hille, Rolf

357 34, 357 35, 357 33, 357 2311, H01L 2702, H01L 2900, H01L 2972, H01L 2906

Patent

active

050619829

ABSTRACT:
A bipolar VLSI process includes masking and patterning, implanting a P+ channel stop (32) and locally oxidizing a P-doped silicon substrate (21) to define a collector region, implanting an N-type collector (43) and diffusing the implants (40, 44). Device emitter, collector and base contact features (64, 66, 68) are photolithographically defined by two openings (54, 56) spaced lengthwise along the collector region. Low resistivity P- and N-type regions (74, 80) are implanted in the substrate in the openings and covered by local oxidation (86, 88). The collector region is preferably formed in a keyhole shape with a wide collector contact feature (66B) and adjoining region 80B and narrow base contact (68B) and emitter (64B) features and intervening region (74B). The substrate (22) is exposed in the emitter and contact features. A single polysilicon layer (94) is deposited, selectively doped and oxidized to form separate base, collector and emitter contacts (94) and a triple diffused NPN transistor (116, 92, 40).

REFERENCES:
patent: 4125853 (1978-11-01), Fulton et al.
patent: 4445268 (1984-05-01), Hirao
patent: 4705599 (1987-11-01), Suda et al.
patent: 4949153 (1990-08-01), Hirao et al.
patent: 4962053 (1990-10-01), Spratt et al.
IBM Technical Disclosure Bulletin, vol. 32, #6B, Nov. 89, pp. 157-159.

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