VLSI integrated circuit having parallel bonding areas

Details VLSI integrated circuit having parallel bonding areas VLSI integrated circuit having parallel bonding areas

1986-03-18

1988-04-12

Edlow, Martin H.

357 40, 357 68, 357 71, H01L 2710, H01L 2348

Patent

active

047378360

ABSTRACT:
A very large scale multicell integrated circuit is provided with significantly improved circuit density. Both active and passive circuit elements are formed in a semiconductor substrate using ordinary diffusion techniques. Connectors, preferably made of polysilicon material, are then formed on the surface of the substrate. The connectors have bonding pad areas located along predetermined lines where metal connectors of later-formed metallization layers can be located. Some of the connectors have bonding pad areas connected to circuit elements while others are left unconnected. The subsequently formed metallization layers can then be used to connect together various ones of the circuit elements and multiple ones of the cells together in any desired circuit configuration using the polysilicon connectors.

REFERENCES:
patent: 3365707 (1968-01-01), Mayhew
patent: 3621562 (1971-11-01), Patel
patent: 3808475 (1974-04-01), Buelow et al.
patent: 3983619 (1976-10-01), Kubo
patent: 4255672 (1981-03-01), Ohno et al.
patent: 4295149 (1981-10-01), Balyoz et al.
patent: 4322821 (1982-03-01), Lohstroh et al.
patent: 4500906 (1985-02-01), Ohno et al.

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