VLSI implementation of metastability-based random number...

Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed

Reexamination Certificate

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Reexamination Certificate

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10801768

ABSTRACT:
A random number generator includes a chain of pairs of D-type flip-flops205, 215. . . having D and L inputs, a chain of substantially identical cascaded upper buffers210,220. . . each having a predetermined delay d1and respective output taps. There is a chain of substantially identical cascaded lower buffers240,260. . . each having a predetermined delay d2, and respective output taps, wherein d1≠d2. A first one of the pair of D-type flip flops205has its D and L inputs connected to a respective output tap of one of the upper buffers210and a respective output tap of one of the lower buffers240, and a second one of the pair of D-type flip flops has its D and L inputs connected to a respective output tap of one of the lower buffers260and a respective output of one of the upper buffers215. The common clock input201is connected to the first inputs of both the cascaded upper buffers and the cascaded lower buffers210, 220. . . and240, 260. . . A metastability detector275,280 285,290,295. . . for each individual flip-flop of the chain of flip flops, and a respective metastability detector connected to the Q output of each respective flip-flop. The metastability detectors have a counting feature to count a number of times that each of the respective metastability detector signals a metastable state, and one flip-flop of the pair flip-flops having the most metastable detector states is selected to generate random numbers from its output.

REFERENCES:
patent: 6631390 (2003-10-01), Epstein
patent: 6771104 (2004-08-01), Hars
patent: 2004/0264233 (2004-12-01), Fukushima et al.
patent: 2004/0267845 (2004-12-01), Hars
patent: 2004/0267846 (2004-12-01), Hars et al.
patent: 2005/0004960 (2005-01-01), Hars
patent: 2005/0004961 (2005-01-01), Hars

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