1994-04-05
1995-11-28
Beausoliel, Jr., Robert W.
Excavating
371 211, 371 213, 371 225, 371 251, G01R 3128, G01R 3126, G01C 2900
Patent
active
054714826
ABSTRACT:
A method for comprehensively testing embedded RAM devices and a means for detecting if any of the cells within the embedded RAM devices have a slow write recovery time. The preferred mode of the present invention utilizes built-in self-test (BIST) techniques for testing the embedded RAM's within a VLSI device. In accordance with the present invention, a modified 5N march test sequence is performed on the embedded RAM devices. The modified 5N March test sequence is a simple algorithm implemented in programmable hardware that has the capability of ensuring that the embedded RAM devices are functional and that they meet the recovery time requirements. The preferred mode of the present invention uses this algorithm to determine if the embedded RAMs are operating properly before the VLSI devices are used in card assembly. However, this method can also be used after card assembly to monitor the embedded RAM's integrity.
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Byers Larry L.
Engel Jeff A.
Fye Philip J.
Maciona Gerald J.
Mackenthun Donald W.
Beausoliel, Jr. Robert W.
Fisch Alan M.
Unisys Corporation
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