VLSI circuit structure for implementing JPEG image compression s

Details VLSI circuit structure for implementing JPEG image compression s VLSI circuit structure for implementing JPEG image compression s

1994-09-07

1997-08-19

Chin, Tommy P.

Television

Bandwidth reduction system

348390, H04N 732, H04N 730

Patent

active

056593627

ABSTRACT:
A fully pipelined VLSI circuit structure for implementing the JPEG baseline image compression standard. The circuit structure exploits the principles of pipelining and parallelism to the maximum extent in order to obtain high speed and throughput. The entire is designed to be implemented on a single VLSI chip to yield a clock rate of about 100 MHz which would allow an input rate of 30 frames per second for 1024.times.1024 color images.

REFERENCES:
patent: 5051840 (1991-09-01), Watanabe et al.
patent: 5101280 (1992-03-01), Moronaga et al.
patent: 5129015 (1992-07-01), Allen et al.
patent: 5189530 (1993-02-01), Fujii
patent: 5253078 (1993-10-01), Balkanski et al.
patent: 5260808 (1993-11-01), Fujii
patent: 5283656 (1994-02-01), Sugahara
patent: 5289577 (1994-02-01), Gonzales et al.
patent: 5295077 (1994-03-01), Fukuoka
patent: 5319724 (1994-06-01), Blonstein et al.
patent: 5339265 (1994-08-01), Liu et al.
patent: 5379351 (1995-01-01), Fandrianto et al.
patent: 5444542 (1995-08-01), Hoshi et al.
patent: 5450599 (1995-09-01), Horvath et al
patent: 5452466 (1995-09-01), Fettweis
patent: 5467131 (1995-11-01), Bhaskaran et al.
Ching-Te Chiu et al, "Real-Time Parallel and Fully Pipelined Two-Dimensional DCT Lattice Structures with Application to HDTV Systems", IEEE Trans. on Cir. and Systems for Video Technology, vol. 2, No. 1, Mar. 1992, p. 25-37.
"VLSI Implementation of a 16.times.16 Discrete Cosine Transform", IEEE Trans. on Cir. & Sys., vol. 36, No. 4, Apr. 1989, pp. 610-617.
"A 100-MHz 2-D Discrete Cosine Transform Core Processor", IEEE Journal of Solid State Circuits, Uramoto et al, vol. 27, No. 4, Apr. 1992, pp. 492-499.
"VLSI Implementation of Single Chip JPEG Codec", Chen et al, IEEE VLSITSA, 1993, pp. 189-193.
"A VLSI Chip for Variable Length Encoding and Decoding", IEEE, Mukherjee et al, 1992, pp. 170-173.

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