VLSI circuit layout method based on spreading functions and simu

Details VLSI circuit layout method based on spreading functions and simu VLSI circuit layout method based on spreading functions and simu

1996-01-05

1998-04-07

Voeltz, Emanuel Todd

Boots, shoes, and leggings

364489, 364490, 364491, G06F 1500

Patent

active

057372330

ABSTRACT:
A VLSI circuit layout method includes defining a circuit to be designed in terms of a set of components V and a set of nets H connecting the components. A cost function is defined using a spreading function to define a cost of a VLSI circuit layout. A simulated annealing is applied to the cost function to produce a VLSI circuit layout having a minimal cost function. The resulting VLSI circuit layout requires minimal area.

REFERENCES:
S. Kirkpatrick entitled, "Optimization by Simulated Annealing," J. Statis. Phy., 34:975-986, 1984.
C. Sechen et al entitled, "An Improved Simulated Annealing Algorithm for Row-Based Placement," Proc. IEEE Int'l. Conf. On Computer-Aided Design, pp. 478 to 481, Nov. 1987.
G. Even et al, entitled "Improved Approximations via Efficient Divide-and-Conquer,"in the Proceedings on the Foundations of Computer Science 95, Oct. 1995.
S.N. Bhatt et al, entitled "A Frame for Solving VLSI Graph Layout Problems," JCSS, vol. 28, pp. 300 to 343, 1984.
C.E. Leiserson, entitled "Area-Efficient VLSI Computation," M.I.T. Press, 1983.

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