VLSI bipolar transistor process

Details VLSI bipolar transistor process VLSI bipolar transistor process

1989-02-21

1991-07-30

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 32, 437 26, 437909, 437917, 148DIG10, 148DIG11, 148DIG96, H01L 21265

Patent

active

050360167

ABSTRACT:
A bipolar VLSI process includes masking and patterning, implanting a P+ channel stop and locally oxidizing a lightly P-doped, monolithic silicon substrate to define a collector region. An N-type collector is implanted and the implants are diffused to form a shallow gradient P-N junction. Then, device emitter, base and collector contact features are photolithographically defined by two openings spaced along the length of the collector region. The collector region is formed in a keyhole shape with a wider end portion encompassed by the collector contact feature and adjoining opening and a narrower opposite end portion which includes the base contact and emitter features and intervening opening. Low resistivity P- and N-type regions are implanted in the substrate in the openings; the openings are covered by local oxidation; and the substrate surface region are exposed in the adjoining contact features. The active transistor and the collector, base and emitter contacts are thereby self-aligned within the collector region. A single polysilicon layer is used to form base, collector and emitter contacts and a triple diffused transistor. Portions of the substrate silicon and polysilicon are locally oxidized to isolate the contacts and to define emitter width. The keyhole shape of the collector region defines collector contact width independently of base contact width and emitter length.

REFERENCES:
patent: 4125853 (1978-11-01), Fulton et al.
patent: 4433471 (1984-02-01), Ko et al.
patent: 4866001 (1989-09-01), Pickett et al.

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