VLSI architecture for a Reed-Solomon decoder

Details VLSI architecture for a Reed-Solomon decoder VLSI architecture for a Reed-Solomon decoder

1990-02-15

1992-07-14

Beausoliel, Robert W.

Excavating

G06F 1110

Patent

active

051309904

ABSTRACT:
A basic single-chip building block for a RS decoder system is partitioned into a plurality of sections the first of which consists of a plurality of syndrome subcells each of which contains identical standard-basis finite-field multipliers that are programmable between 10-bit and 8-bit operation. A desired number of basic building blocks may be assembled to provide a RS decoder of any syndrome subcell size that is programmable between 10-bit and 8-bit operation.

REFERENCES:
patent: 4653052 (1987-03-01), Doi
patent: 4835775 (1989-05-01), Seroussi
patent: 4907233 (1990-03-01), Deutsch
G. Maki, et al., "VLSI Reed-Solomon Decoder Design," Proceedings of the Military Communications Conference (Milcom), Monterey, Calif., pp. 46.5.1-46.5.6, Oct. 5-9, 1986.
I. S. Hsu, et al., "A Comparison of VLSI Architecture for Time and Transform Domain Decoding of Reed-Solomon Codes," TDA Progress Report, 42-92, vol. Oct.-Dec. 1987, Jet Propulsion Laboratory, Pasadena, Calif., pp. 63-81, Feb. 15, 1988.
I. S. Hsu, et al., "A Comparison of VLSI architectures of Finite Field Multipliers Using, Dual, Normal or Standard Basis," IEEE Trans. on Computers, vol. 37, 1988.
P. A. Scott, et al., "A Fast Multiplier for GS(2.sup.m)," IEEE Journal on Selected Areas in Communications, vol. SAC-4, No. 1, Jan. 1986.
I. S. Hsu et al., "A New VLSI Architecture for a Single-Chip Type Reed-Solomon Decoder" TDA Progress Report 42-96, Oct.-Dec. 1988.

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