Boots – shoes – and leggings
Patent
1993-10-25
1995-09-12
Bowler, Alyssa H.
Boots, shoes, and leggings
395800, 3649314, 36493141, 36493142, 364938, 3649381, 364DIG2, G06F 1516, G06F 928
Patent
active
054505569
ABSTRACT:
A highly parallel and pipelined computer processor such as a pipelined very long instruction word (VLIW) processor having a plurality of arithmetic and logic units (ALUs) which process computer operations in parallel to speed up the operation of the computer. Operations issued during the branch delay period following conditional jump operations are conditioned on the outcomes of the condition evaluation of such conditional jump operations that have not yet percolated through the instruction issue pipeline, by matching a field in the operation to path information generated by a branch control unit. Operations that succeed are allowed to proceed and the effects of unsuccessful operations are disabled. This allows a form of look-ahead computation after a conditional branch which is particularly attractive for a VLIW processor having a large number of parallel functional units and allows useful work to be done in the branch delay periods. Optionally, only such operations that affect the programmer-visible state of the computer are so conditioned, e.g., store operations to memory, program flow control operations and operations that raise exception conditions. The matching algorithm can be implemented such that an operation is enabled on a single path or on an arbitrary set of paths.
REFERENCES:
patent: 3611306 (1971-10-01), Reigel et al.
patent: 3781814 (1973-12-01), Deerfield et al.
patent: 4833599 (1989-05-01), Colwell et al.
patent: 4920538 (1990-04-01), Chan et al.
patent: 4943912 (1990-07-01), Aoyama et al.
patent: 5050068 (1991-09-01), Dollas et al.
patent: 5127092 (1992-06-01), Gupta et al.
patent: 5179680 (1993-01-01), Colwell et al.
patent: 5203002 (1993-04-01), Wetzel
patent: 5313551 (1994-05-01), Labrousse et al.
patent: 5355460 (1994-10-01), Eickemeyer et al.
DeGloria, "A Programmable Instruction Format Extension to VLIW Architectures", 1992, IEEE Computer. Soc. Press, (Abstract Only).
Labrousse et al, "A 500 MHZ Microprocessor with a Very Long Inst. Word Architecture"; 1990, IEEE International Solid-State Circuits Conference (Abstract Only).
Kemal Ebcioglu, "Some Design Ideas for a VLIW Architecture for Sequential-Natural Software"; 1988, Elsevier Science Publishers.
Abnous et al, "Special Features of a VLIW Architecture", Feb. 1991, Department of Electrical and Computer Engineering University of California, Irvine.
"A Programmable Instruction Format Extension to VLIW Architectures"; by Alexander De Gloria; IEEE, Mar. 1992, pp. 35-40.
"Harp: A VLIW RISC Processor"; by P. A. Findlay et al; IEEE May 1991; pp. 368-372.
Harp: A Parallel Pipelined RISC Processor; G. B. Steven et al, Microprocessors and Microsystems, Nov., No. 9, London, GB.
Nicolau et al., "Rope: A Statically Scheduled Supercomputer Architecture", Proceedings 1st International Conference on Supercomputing Systems, Dec. 16, 1985 pp. 158-168.
R. D. Dowsing et al., "Programming a Bounded Buffer using the Object and Path Expression Constructs of Path Pascal", The Computer Journal, vol. 29, No. 5, 1986, pp. 423-429.
J. Basu et al., "Ordered Ports--a Language Concept for High-level Distributed Programming", The Computer Journal, vol. 30, No. 6, 1987, pp. 487-497.
E. W. Dijkstra et al., "Guarded Commands, Nondeterminacy and Formal Derivation of Programs", Programming Languages, T. A. Standish--Editor, pp. 453-457.
J. A. Fisher, Proceedings of the 10th Annual Symposium on Computer Architecture, Jun. 1983 "Very Long Instruction Word Architecture and the ELI-512".
R. P. Colwell et al, Proceedings of ASPLOS, 1987 "A VLIW Architecture for a Trace Scheduling Compiler".
P. Y.-T. Hsu, Thesis, University of Illinois at Urbana-Champaign, 1986.
S. Borkar et al, "iWarp: Integrated Solution to High Speed Parallel Computing", IEEE Proceedings on Supercomputing, pp. 330-339, 1988 Catalog #88CH2617-9.
R. M. Tomasulo, "An Efficient Algorithm for Exploiting Multiple Arithmetic Units", IBM Journal of Research and Development, vol. 11, pp. 25-33, Jan. 1967.
J. A. Fisher, IEEE Transactions on Computers, vol. C-30, pp. 478-490 Jul. 1981.
B. R. Rau et al, Proceedings of the 9th Annual International Symposium on Computer Architecture, pp. 131-139, 1982 "Efficient Code Generation for Horizontal Architectures".
K. Ebcioglu, Proceeding of the IFIP Working Conference on Parallel Processing, Pisa Italy, Apr. 1988, "Some Design Ideas for a VLIW Architecture for Sequential-Natured Software".
Gregory R. Andrews et al, Computer Surveys, vol. 15, No. 1, Mar. 1983 "Concepts and Notations for Concurrent Programming".
Technical Summary, Multiflow Computer, Inc., Jun. 23, 1987.
Peter Yan Tek Hsu, "Highly Concurrent Scalar Processing" University of Illinois at Urbana-Champaign, Jan. 1986.
Scott McFarling and John Hennessy, "Reducing the Cost of Branches" pp. 396-403, 1986 IEEE.
Labrousse Jean-Michel J.
Slavenburg Gerrit A.
An Meng-Ai T.
Barschall Anne E.
Bowler Alyssa H.
North American Philips Corporation
LandOfFree
VLIW processor which uses path information generated by a branch does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with VLIW processor which uses path information generated by a branch, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and VLIW processor which uses path information generated by a branch will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-413359