Electrical computers and digital processing systems: processing – Processing architecture – Long instruction word
Reexamination Certificate
1999-09-29
2002-12-24
Pan, Daniel H. (Department: 2183)
Electrical computers and digital processing systems: processing
Processing architecture
Long instruction word
C712S212000, C712S228000, C711S125000
Reexamination Certificate
active
06499096
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to VLIW (Very Long Instruction Word) processors and more particularly to a VLIW processor which executes a compressed program code, a code compression device which compresses a program code, a code compression method, and a medium on which a code compression program is recorded.
2. Description of the Background Art
There have been increasing demands for improved processor performance in various fields such as multimedia processing and high resolution image processing. However, the current LSI (Large Scale Integration) manufacturing technique has a limit in attaining higher device speed. Therefore, VLIW processors have been drawing attention and actively researched and developed.
The VLIW processor which contains a plurality of processing units aims to improve the performance of a program-controlled processor by executing a plurality of instructions in the same cycle and thus increasing parallelism. In the VLIW processor, a processing unit corresponding to an instruction field is predetermined and therefore not all the instruction slots are filled with valid instructions. Thus, a nop (no operation) instruction, as an invalid instruction, is inserted in a code, resulting in the essential problem of low code density.
The VLIW processor in which two instructions are simultaneously issued cannot simultaneously execute “load mem (100)→R1” and “add R1, R2→R3” as shown in code example 1 below.
Code Example 1
instruction sequence for
instruction sequence for
code number
left sub-instructions
right sub-instructions
1
store R0 → mem (200)
:sub R4, R5 → R6
2
load mem (100) → R1
:nop
3
nop
:add R1, R2 → R3
Since one of them is an instruction to load a value to a register R1 and the other is an instruction to refer to the value of the same register R1, the instructions cannot be executed at the same time. In this case, a nop instruction is inserted as shown in code example 1. In the following description, a long instruction formed by combining two instructions is called a VLIW instruction and each instruction included in the VLIW instruction (load, nop and add instructions in code example 1) is called a sub-instruction.
Inventions disclosed in H. Sato, T. Yoshida, M. Matsuo, T. Kengaku and K. Tsuchihashi; “A Dual-Issue RISC Processor for Multimedia Signal Processing,” IEICE Trans. Electron., vol. E81-C, No. 9, September 1998 and Japanese Patent Laying-Open No. 9-84004 aim to solve the problem above. According to these inventions, code compression is carried out by separating a VLIW instruction, which includes instructions to be executed originally at the same time, into two sub-instructions and executing the sub-instructions. In other words, “load mem (100)→R1” and “add R1, R2→R3” are described as one VLIW instruction, and the VLIW instruction is divided into two cycles during execution to separately execute the sub-instructions as shown in code example 2 below.
Code Example 2
instruction sequence for
instruction sequence for
code number
left sub-instructions
right sub-instructions
1
store R0 → mem (200)
:sub R4, R5 → R6
2
load mem (100) → R1
:add R1, R2 → R3
For this operation, FM (Format-Specifying) bits are assigned to lower order two bits of the 32-bit VLIW instruction, and the instruction is executed by processor in the following manner according to the FM bit pattern.
(1) FM=00: simultaneously execute two sub-instructions
(2) FM=01: execute the left sub-instruction and then execute the right sub-instruction
(3) FM=10: execute the right sub-instruction and then execute the left sub-instruction
(4) FM=11: execute two sub-instructions by regarding the two sub-instructions as one long instruction
Since the operation mode in the case of FM=11 is irrelevant to the present invention, it will not be described in detail.
FIG. 1
schematically shows relations between FM bits and instruction execution.
Code example 1 is described as code example 3 below.
Code Example 3
instruction sequence for
instruction sequence for
code number
FM
left sub-instructions
right sub-instructions
1
00
store R0 → mem (200)
:sub R4, R5 → R6
2
01
load mem (100) → R1
:add R1, R2 → R3
In executing code example 3, a processor executes instructions as shown in execution sequence example 1.
Execution Sequence Example 1
instruction sequence for
instruction sequence for
step number
left sub-instructions
right sub-instructions
1
store R0 → mem (200)
:sub R4, R5 → R6
2
load mem (100) → R1
:
2′
:add R1, R2 → R3
In the 2nd cycle, an arithmetic unit corresponding to the add instruction assumes the non-operation state and carries out substantially the same operation as execution of the nop instruction. In the 2'nd cycle, an arithmetic unit corresponding to the load instruction assumes the non operation state and carries out substantially the same operation as execution of the nop instruction. Therefore, execution sequence example 1 is equivalent to execution of code example 1. Since instructions are stored in an instruction memory in the format of code example 3, they are compressed to 2/3 times the capacity compared with code example 1.
In the conventional VLIW processor above, the order of describing sub-instructions can be determined more freely and the code density can be improved by adding FM bits to a VLIW instruction. Since the FM bits are assigned to two bits of an instruction field, however, the number of instruction types is limited. Further, instructions need to be mapped prior to instruction decoding, which increases circuit delay.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a VLIW processor capable of processing a compressed program in such an execution sequence that is taken prior to compression without assigning special bits to an instruction field.
Another object of the present invention is to provide a VLIW processor, which corresponds to the VLIW method of at least 3-ways, capable of processing a compressed program in such an execution sequence that is taken prior to compression.
Still another object of the present invention is to provide a VLIW processor, which corresponds to the 2n-way VLIW method, capable of processing a compressed program in such an execution sequence that is taken prior to compression.
Still another object of the present invention is to provide a code compression device capable of compressing a program described by a VLIW instruction.
Still another object of the present invention is to provide a code compression method capable of compressing a program described by a VLIW instruction.
Still another object of the present invention is to provide a medium on which a code compression program capable of compressing a program described by a VLIW instruction is recorded.
According to one aspect of the present invention, a VLIW processor includes a plurality of containers, an exchanging portion exchanging a plurality of sub-instructions and inputting the instructions to the plurality of containers, a plurality of decoders connected to the plurality of containers, and a plurality of processing units connected to the plurality of decoders.
Since the exchanging portion exchanges a plurality of sub-instructions and inputs them to the plurality of containers, a compressed code can be executed in such an execution sequence that is taken prior to compression.
According to another aspect of the present invention, a code compression device includes an extracting portion extracting consecutive VLIW instructions from a source code, and a compressing portion compressing the consecutive VLIW instructions based on a nop instruction included in the consecutive VLIW instructions extracted by the extracting portion.
Since the compressing portion compresses the consecutive VLIW instructions based on a nop instruction included in the consecutive VLIW instructions extracted by the extracting portion, a program described by a VLIW instruction can be compre
McDernott, Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Pan Daniel H.
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