Electrical computers and digital processing systems: processing – Processing architecture – Long instruction word
Reexamination Certificate
2006-07-18
2006-07-18
Tsai, Henry W. H. (Department: 2183)
Electrical computers and digital processing systems: processing
Processing architecture
Long instruction word
C712S215000
Reexamination Certificate
active
07080234
ABSTRACT:
According to the invention, a processing core (12) comprising a processing pipeline (100) having N-number of processing paths (56), each of which process instructions (54) on M-bit data words. In addition, the processing core (12) includes one or more register files (60), each preferably having Q-number of registers which are M-bits wide. Preferably, one of the Q-number of registers in at least one of the register files (60) is a program counter register dedicated to hold a program counter, and one of the Q-number of registers in at least one of the register files is a zero register dedicated to hold a zero value. In this manner, program jumps can be executed by adding values to the program counter in the program counter register, and memory address values can be calculated by adding values to the program counter stored in the program counter register or to the zero value stored in the zero register.
REFERENCES:
patent: 4725945 (1988-02-01), Kronstadt et al.
patent: 4894770 (1990-01-01), Ward et al.
patent: 4980819 (1990-12-01), Cushing et al.
patent: 5184320 (1993-02-01), Dye
patent: 5261066 (1993-11-01), Jouppi et al.
patent: 5301340 (1994-04-01), Cook
patent: 5317718 (1994-05-01), Jouppi
patent: 5386547 (1995-01-01), Jouppi
patent: 5530817 (1996-06-01), Masubuchi
patent: 5553095 (1996-09-01), Engdahl et al.
patent: 5564035 (1996-10-01), Lai
patent: 5588130 (1996-12-01), Fujishima et al.
patent: 5623627 (1997-04-01), Witt
patent: 5649154 (1997-07-01), Kumar et al.
patent: 5650955 (1997-07-01), Puar et al.
patent: 5687338 (1997-11-01), Boggs et al.
patent: 5703806 (1997-12-01), Puar et al.
patent: 5710907 (1998-01-01), Hagersten et al.
patent: 5900011 (1999-05-01), Saulsbury et al.
patent: 5953738 (1999-09-01), Rao
patent: 6000007 (1999-12-01), Leung et al.
patent: 6092175 (2000-07-01), Levy et al.
patent: 6128700 (2000-10-01), Hsu et al.
patent: 6128702 (2000-10-01), Saulsbury et al.
patent: 6202143 (2001-03-01), Rim
patent: 6256256 (2001-07-01), Rao
patent: 6275900 (2001-08-01), Liberty
patent: 6321318 (2001-11-01), Baltz et al.
patent: 6332215 (2001-12-01), Patel et al.
patent: 6338160 (2002-01-01), Patel et al.
patent: 6366999 (2002-04-01), Drabenstott et al.
patent: WO 00/33178 (2000-06-01), None
U.S. Appl. No. 60/187,738.
Stallings W. “Computer Organization and Architecture”, 1996, Prentice Hall, 4th edition, pp. 53-55.
Numomura Y et al: “M32R/D-Integrating DRAM and Microprocessor” IEEE Micro, IEEE Inc. New York, US, vol. 17, No. 6, Nov. 1, 1997, pp. 40-48, XP000726003; ISSN: 0272-1732.
Kozyrakis C E et al: “Scalable Processors in the Billion-Transistor Era: IRAM” Computer, IEEE Computer Society, Long Beach., CA, US, US vol. 20, No. 0 Sep. 1, 1997, pp. 75-78, XP00073003; ISSN: 0018-9162.
Herrmann Klaus, Hilgenstock Joerg, Pirsch Peter: “Architecture of a Multiprocessor System with Embedded DRAM for Large Area Integration” Oct. 8, 1997, IEEE International Conference on Innovative Systems in Silicon, Piscataway, NJ, USA; XP002179990.
Aimoto, Yoshiharu et al.; “A.768GIPS 3.84GB/s 1 W Parallel Image-Processing RAM Integratng a 16 Mb DRAM and 128 Processors”; ISSCC96/Session 23 / DRAM / Paper SP23.3; 1996 IEEE International Solid-State Circuits Conference; pp. 372-373 and 476.
Bursky, Dave; “Combo RISC CPU and DRAM Solves Data Bandwidth Issues”; Electronic Design; Mar. 4, 1996; pp. 67-71.
Saulsburg, Ashley, et al., “Missing the Memory Wall: The Case for Processor/Memory Integration”; ACM; 1996; pp. 90-101.
Shimizu, Toro, et al.; “A Multimedia 32b RISC Microprocessor with 16 Mb DRAM”; ISSCC96/Session 13 / Microprossors/Paper FP 13.4; 1996 IEEE International Solid State Circuits Conference; pp. 216-217 and 448.
Mitsubishi Electric Corp; Product Specification for Single-Chip 32-Bit CMOS Microcomputer, © May 1998.
Emberson David R.
Nettleton Nyles
Parkin Michael
Saulsbury Ashley
Townsend and Townsend / and Crew LLP
Tsai Henry W. H.
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