Electrical computers and digital processing systems: processing – Processing architecture – Long instruction word
Reexamination Certificate
2006-01-17
2006-01-17
Tsai, Henry W. H. (Department: 2183)
Electrical computers and digital processing systems: processing
Processing architecture
Long instruction word
C712S022000
Reexamination Certificate
active
06988181
ABSTRACT:
According to the invention, a processing core is disclosed. The processing core includes one or more processing pipelines and a number of register flies. The processing pipelines having a total of N-number of processing paths, where each of the processing paths processes instructions on M-bit data words. Each of the number of register files has Q-number of registers that are each M-bits wide. The Q-number of registers within each of the plurality of register files are either private or global registers. When a value is written to one of said Q-number of said registers, which is a global register within one of said number of register files, the value is propagated to a corresponding global register in the other of the number of register files. When a value is written to one of said Q-number of the registers, which is a private register within one of said number of register files, the value is not propagated to a corresponding register in the other of said number of register files.
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Parkin Michael
Rice Daniel S.
Saulsbury Ashley
Townsend and Townsend / and Crew LLP
Tsai Henry W. H.
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