Pulse or digital communications – Receivers – Particular pulse demodulator or detector
Reexamination Certificate
2000-12-21
2004-01-06
Tran, Khai (Department: 2631)
Pulse or digital communications
Receivers
Particular pulse demodulator or detector
C714S794000
Reexamination Certificate
active
06674816
ABSTRACT:
BACKGROUND OF THE INVENTION
This application incorporates by reference Taiwan application Serial No. 89116291, filed Aug. 11, 2000.
1. Field of the Invention
The invention relates in general to a Viterbi detector for extending tolerable extent of direct current (DC) bias, and more particularly to a Viterbi detector, used in a partial response maximum likelihood (PRML) signal processing apparatus, for extending the tolerable extent of the DC bias.
2. Description of the Related Art
There are many approaches to the storage of information code in a recording medium. For the increasing the data access density, partial response maximum likelihood (PRML) signal processing is widely used in optical disk systems.
In the process of transmitting signals, when the channel bandwidth is lower than the bandwidth of the signals transmitted in the channel, inter-symbol interference (ISI) occurs in adjacent bits of the signals in the receiving end. When ISI is serious, it may cause jitter. As the recording density of optical disks increases, jitter caused by ISI becomes more serious, increasing the difficulty in phase-locking. For overcoming this phenomenon, the principle of partial response (PR) channel is applied. In PRML signal processing, the channel response is appropriately equalized in a channel response in terms of a PR polynomial. In this way, ISI is constrained and is in an expectable characteristic, resulting in reduction of jitter when ISI occurring. Thus, the performance of phase-locking is improved. In other words, PRML is potentially a technique of improving the recording density of optical disks.
Referring to
FIG. 1
, it illustrates a PRML signal processing apparatus in block diagram form. In
FIG. 1
, modulated information code E is first inputted into a return-to-zero inversion (NRZI) circuit
102
. The modulated information code signal E is then processed by an exclusive-OR gate
104
and a delay element
106
of the NRZI circuit
102
, resulting in an output signal F of the NRZI circuit. After that, the output signal F of the NRZI circuit is written to a recording medium
108
, such as an optical disk. In addition, PR(1, 2, 1) equalization of the output signal F of the NRZI circuit is performed, where the minimum code reversal distance &dgr;=2.
Referring now to
FIG. 2
, it illustrates the waveforms of the signals involved in
FIG. 1
including the information code signal E, output signal F of the NRZI circuit, reproduce signal G, output signal J of the PR equalizer and output signal Z of the Viterbi detector, and the corresponding pits on the optical disk. In
FIG. 2
, the bit sequence in (a) corresponds to an example the information code signal E while the bit sequence in (b) illustrates the corresponding output signal F of the NRZI circuit. When the information code signal E has a signal level change of rising edge, the signal Z has a signal level change of itself as well; otherwise, the signal level of the signal Z remains unchanged. The signal in (c) is the LD driving signal produced according to the signal F and is used for controlling a LD (not shown in Figures) to perform write operation on the optical disk. Illustration in (d) is to show the pits on the optical disk which the LD performs the write operation on. The signal of (e) is the reproduce signal G corresponding to the data read from the optical disk by using the optical head. The signal of (f) is the output signal J of the PR equalizer
110
after the PR(1, 2, 1) process. And the signal of (g) is the output signal Z of the Viterbi detector
112
obtained after processing the signal J. The PR equalizer
110
and Viterbi detector
112
are called a reproduction signal processing unit
114
.
In
FIG. 2
, when the signal F is in a 1 state, the LD driving signal is in the high level. Accordingly, a pit is produced on the optical disk. The reproduction signal processing unit
114
is used for generating the signal Z by the Viterbi detector using the reproduce signal G. The signal Z is theoretically identical to the information code signal E.
Referring to
FIG. 3
, it illustrates the Viterbi detector
112
in
FIG. 1
in block diagram form. The Viterbi detector includes a branch metric calculation circuit
302
, an add-compare-and-select (ACS) circuit
304
and a path memory unit
306
. The branch metric calculation circuit
302
is for receiving the output signal J of the PR equalizer and calculating the values B000
1
, B000
2
, B001
1
, B011
1
, B100
1
, B110
1
, B111
1
, and B111
2
, called the branch metrics. The ACS circuit
304
is for outputting a path memory control signals H000 and H111 based on the branch metrics above. The path memory unit
306
is controlled by the path memory control signals H000 and H111, outputting the output signal Z of the Viterbi detector.
FIG. 4
is a block diagram of the branch metric calculation circuit
302
in FIG.
3
. The branch metric calculation circuit
302
includes four subtractors
402
, four multiplier
404
, and four registers
406
. In
FIG. 4
, the subtractors
402
respectively calculate J-0, J-0.25, J-0.75, and J-1. Next, the outputs of the subtractors are respectively processed by the multiplers
404
for obtaining the respective squares. Then, the four squares of the difference of the PR equalizer output signal J and four equalization-aimed values {0, 0.25, 0.75, 1} are stored in the delay units
406
respectively. The branch metric calculation circuit
302
outputs the branch metrics B000
1
, B000
2
, B001
1
, B011
1
, B100
1
, B110
1
, B111
1
, and B111
2
respectively. For each point of time, the branch metrics are as follows:
B
000
1
=B
000
2
=(0
−J
)
2
,
B
001
1
=B
100
1
=(0.25
−J
)
2
,
B
011
1
=B
110
1
=(0.75
−J
)
2
,
and
B
111
1
=B
111
2
=(1.0
−J
)
2
.
Referring now to
FIG. 3
, the branch metrics are inputted into the ACS circuit
304
. The branch metrics represent the degree and nearness of the PR equalizer output signal J obtained from the PR(1, 2, 1) equalization of the reproduce signal, and the ideal PR(1, 2, 1) equalization signal.
The ACS circuit
304
uses six path metrics, P000, P001, P011, P100, P110, and P111, and the initial values of them are set to zero. The ACS circuit
304
derives the path metric at time t from the path metric and performs comparison of P000(t)+B000
1
(t) and P100(t)+B100
2
(t) as well as P011(t)+B111
1
(t) and P111(t)+B111
2
(t). From this, the ACS determines and outputs the path control signals H000(t) and H111(t).
Further, the ACS circuit
304
updates the values of the path metrics P000(t+1), P001(t+1), P011(t+1), P100(t+1), P110(t+1), and P111(t+1) according to the following expressions:
P
000(
t
+1)=min{
P
000(
t
)+
B
000
1
(
t
),
P
100(
t
)+
B
000
2
(
t
)},
P
001(
t
+1)=
P
000(
t
)+
B
001
1
(
t
),
P
011(
t
+1)=
P
001(
t
)+
B
011
1
(
t
),
P
100(
t
+1)=
P
110(
t
)+
B
100
1
(
t
),
P
110(
t
+1)=
P
111(
t
)+
B
110
1
(
t
),
and
P
111(
t
+1)=min{
P
011(
t
)+
B
111
1
(
t
) and
P
111(
t
)+
B
111
2
(
t
)}.
The path control signal H000 and H111 are respectively inputted into the path memory unit
306
. The path memory unit
306
stores signal level transition patterns of the output signal J of the PR equalizer corresponding to each point of time in the form of a trellis. In addition, the path memory unit
306
only outputs binary signals. Moreover, when the PR equalizer's output signal J has noise, the Viterbi detector
112
selects the nearest signal level transition pattern according to the path control signals H000 and H111 for each point of time and stores the selected transition patterns in the path memory unit
306
.
In another aspect, path metrics corresponds to the cost of a transition from the state at time t−1 to the state at time t. In this way, the Viterbi detector
112
is to calculate the cost of each path throug
Acer Laboratories Inc.
Bednarek Michael D.
Shaw Pittman LLP
Tran Khai
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