Pulse or digital communications – Receivers – Particular pulse demodulator or detector
Reexamination Certificate
2000-06-14
2004-02-24
Ghebretinsae, Temesghen (Department: 2631)
Pulse or digital communications
Receivers
Particular pulse demodulator or detector
C375S262000, C714S795000, C714S796000
Reexamination Certificate
active
06697442
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a Viterbi decoding apparatus.
As an error-correcting method of performing error correction in the digital transmission of data, there is known, for example, a Viterbi decoding algorithm (G. D. Forney. Jr., “The Viterbi algorithm” Proceeding of IEEE, vol. 61, pp 268-278, Mar. 1973).
In a conventional Viterbi decoding apparatus, as will be described later, the operation of tracing the path memory back to the past every symbol time is performed. As a result, the trace-back operation needs a larger amount of time therefore. Therefore, the apparatus has the problem that the decoding period of time becomes resultantly long.
SUMMARY OF THE INVENTION
An object of the invention is to provide a Viterbi decoding apparatus capable of shortening a decoding process time duration.
According to this invention, there is provided a Viterbi decoding apparatus for processing received P data and received Q data by a trace-back method to obtain decoded data. The received P data and the received Q data are obtained by carrying out convolutional coding of data which are received by the receiver. The Viterbi decoding apparatus comprises branch metric producing means for producing a branch metric in accordance with the received P data and the received Q data, path metric register means for registering a cumulative metric of survivor paths, Add Compare Select (ACS) circuit means for adding said branch metric entering that state to said cumulative metric of the connecting survivor for all the paths entering a state, comparing, selecting the largest metric for each state (in the case constraint length equals to K, the number of the states is the K−1)th power of 2), outputing path-selecting information of each state every symbol time, and storing the selecting metric for each state as the cumulative metric (path metric) of the next preceding time unit, maximum path state number detector means for getting the state number to check the largest path metric among said the states, a plurality of path memory blocks for storeing the path-selecting information of each state every symbol time, the path memory blocks being connected to one another so that a result of trace-back may become a starting point for starting said trace-back of a next path memory block when the trace-back is made, and selector means for selecting outputs of the path memory blocks to produce the decoded data.
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Japanese Office Action, dated Oct. 3, 2001, with English language translation of Japanese Examiner's comments.
Forney, G. D., “The Viterbi Algorithm,”Proceedings of the IEEE, vol. 61, No. 3, Mar. 1973, pp. 268-278.
Ghebretinsae Temesghen
NEC Corporation
Whitham Curtis & Christofferson, P.C.
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