1992-11-06
1995-04-25
Gordon, Paul P.
Excavating
371 44, 371 45, G06F 1110, H03M 1312
Patent
active
054105552
ABSTRACT:
A Viterbi decoding apparatus capable of decoding convolutional codes of 30 Mbps or more in information quantity for such applications as high-definition television broadcasting. The apparatus comprises a path memory circuit and an ACS.SM normalizing circuit. The path memory circuit is made of path memory cells arranged in matrix fashion for shifting a path decoded word in units of a plurality of time slots in accordance with a transition diagram corresponding to that plurality of time slots and on the basis of path selection signals from the ACS.SM circuit that calculates data in units of that plurality of time slots.
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patent: 5117427 (1992-05-01), Miyake et al.
Gerhard Fettweis ("High-Rate Viterbi Processor: A Systolic Array Solution" IEE Journal on Selected Areas in Communications, vol. 8, No. 8, Oct. 1990).
Patent Abstracts of Japan vol. 12, No. 452 (E-687) 28 Nov. 1988 & JP-A-63 178 626 (Fufitsu Limited) 22 Jul. 1988.
Patent Abstracts of Japan vol. 13, No. 323 (E-791) 21 Jul. 1989 & JP-A-10 89 878 (Sony Corp) 5 Apr. 1989.
Patent Abstracts of Japan vol. 14 No. 73 (E-887) 9 Feb. 1990 & JP-A-12 91 527 (Fufitsu Limited) 24 Nov. 1989.
Patent Abstracts Of Japan vol. 9, No. 10 (E-290) 17 Jan. 1985 & JP-A-59 160 349 (Fujitsu K.K.) 11 Sep. 1984.
Itakura Eisaburo
Kojima Yuichi
Frommer William S.
Gordon Paul P.
Moise Emmanuel
Sinderbrand Alvin
Sony Corporation
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