Viterbi decoding apparatus

Details Viterbi decoding apparatus Viterbi decoding apparatus

1992-11-12

1994-03-01

Chin, Stephen

Pulse or digital communications

Repeaters

Testing

371 43, H04L 2706

Patent

active

052915247

ABSTRACT:
A Viterbi decoding apparatus for decoding received data by Viterbi decoding comprising a state metric memory circuit, a path memory circuit, and a path decode word decision circuit. The state metric memory circuit stores state metric information obtained by ACS (Adder, Comparator, Selector) processing. The path memory circuit stores path selection information provided by the ACS processing. The path decode word decision circuit weights a plurality of bits with a path decode word of each state according to its degree of likelihood based on state metric information supplied from the state metric memory circuit, cumulatively adding each path decode word obtained by the weighting operation, and comparing a cumulative value obtained by the cumulative adding operation with a preset threshold value to determine decode words. This setup provides sufficiently reliable decode words by a small amount of hardware and in a short processing time to decode, within an average information rate, convolutional codes having information amounting to 30 Mbps or more used in high-definition TV etc.

REFERENCES:
patent: 5050191 (1991-09-01), No
patent: 5081651 (1992-01-01), Kubo
patent: 5099499 (1992-03-01), Hammar
patent: 5155744 (1992-10-01), Ringlehaan

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