Pulse or digital communications – Receivers – Particular pulse demodulator or detector
Reexamination Certificate
2000-12-13
2004-10-26
Chin, Stephen (Department: 2634)
Pulse or digital communications
Receivers
Particular pulse demodulator or detector
C375S316000
Reexamination Certificate
active
06810095
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a branch metric calculation method and a Viterbi decoder in Viterbi decoding in which a branch metric is derived by comparing a codeword produced from a convolutional code with a sign in determination data obtained from conversion of received data for branch metric calculation.
2. Description of the Related Art
Conventionally, in mobile stations in digital cellular mobile telephone systems of a TDMA scheme or a CDMA scheme and digital satellite communication of the CDMA scheme, errors arising in transmission paths are corrected with an error correcting code for obtaining desired channel quality. In the processing with the error correcting code, error bits are detected for correction. The code for the correction is broadly divided, based on methods of random error correction, into a block code or a convolutional code and a concatenated code in which the block code and convolutional code are combined.
Viterbi decoding is well known as decoding at a receiving part for the convolutional code (see Literature “Digital Satellite Communication,” Kazunori Tamura and Tatsuro Masamura, The Telecommunications Association). The Viterbi decoding is an algorithm which can efficiently perform maximum likelihood decoding with the convolutional code by selecting the path closest to the received sequence from two paths joining from certain states. The Viterbi decoding has a relatively high ability for correcting errors arising in transmission paths, and produces high coding gain in combination with a Soft-Decision Decoding scheme. The Viterbi decoding, however, involves large processing and circuit scales, and reductions thereof are problems to be tackled.
Branches are produced corresponding to states of respective node decoders in a tree representation which is a representation for the convolutional code. Specifically, the tree representation is a trellis representation for showing changes in states of independent coders in which two branches are produced corresponding to state 0 or state 1 for input 1 bit. From the trellis, metrics are calculated for providing certainty of paths or branches. In the branch metric calculation method, a codeword of each state produced from the convolutional code is compared with a sign in determination data, and if they match, it is determined that the associated metric is 0, or if they do not match, the metrics of the determination data are added to calculate a branch metric.
FIG. 1
is a circuit diagram showing a configuration for performing conventional branch metric calculation. In
FIG. 1
, description is made on the assumption that the coding rate is ⅓ and the number of states is 256.
Metric data 1, 2 and 3 are supplied to latch circuits
26
a
,
26
b
and
26
c
, respectively. Latch circuits
26
a
to
26
c
hold metric data 1 to 3, respectively, until latch pulses are supplied thereto. After the latching, latch circuits
26
a
to
26
c
output metric data of K bits for state N. Inverters
27
a
,
27
b
and
27
c
invert the metric data of K bits for N state to metric data of k bits for state N+128 before output.
The metric data of K bits for state N and the metric data of k bits for state N+128 are supplied to time-division switches
28
a
,
28
b
and
28
c
. Time-division switches
28
a
to
28
c
switch to select and output the metric data for state N or the metric data for state N+128, respectively, in accordance with timing pulses.
The aforementioned number of states 256 is a typical value for the number of states in the Viterbi decoding in a digital cellular mobile telephone system or the like. The number “128” in the metric data of k bits for state N+128 is equal to ½ of the number of states 256 for a butterfly structure in state transition in the Viterbi decoding, later described in FIG.
4
.
The metric data for state N or the metric data for state N+128 selected by time-division switches
28
a
to
28
c
are supplied to word split circuits
29
a
,
29
b
and
29
c
, respectively. Word split circuits
29
a
to
29
c
divide the metric data for state N or the metric data for state N+128 into signs and metrics before output, respectively. The sign of 1 bit separated at each of word split circuits
29
a
to
29
c
is supplied to each of EX-OR (exclusive OR) gates
33
a
to
33
c
. EX-OR gates
33
a
to
33
c
also receive codewords (g0, g1 and g2) for each state obtained from processing in convolutional code generator
35
, and counter (N=0 to 127)
34
, and make determination about the signs with EX-OR operations.
In accordance with the outputs from EX-OR gates
33
a
to
33
c
, selectors
30
a
,
30
b
and
30
c
select the metrics from word split circuits
29
a
to
29
c
or 0 (Z). The selected outputs are added at adders
32
a
and
32
b
to calculate a branch metric.
The Viterbi decoding for performing such branch metric calculation involves large processing and circuit scales as compared with processing of threshold decoding in block coding (for example, with BHC code or Golay code) and in convolutional coding or the like, and reductions thereof are problems to be tackled. Thus, various proposals have been made for reducing the processing and circuit scales.
As one of the proposals, in a prior art of “Viterbi Decoder” in Japanese Patent Laid-open Publication No.6-303153, outputs from branch metric operation means which are supplied to an ACS (Add/Compare/Select) unit are controlled in a time-division manner for reducing the circuit scale of the Viterbi decoder. For maximum likelihood determination in maximum likelihood determination means, outputs from path metric resistors are processed in a time-division manner at compare/select circuits in the ACS unit. The scale of the maximum likelihood determination means is thus reduced to reduce the processing and circuit scales of the Viterbi decoder.
In a prior art of “Branch Metric Operation Circuit” in Japanese Patent Laid-open Publication No.7-131494, for reducing the processing and circuit scales resulting from the reduced number of bits in a branch metric operation circuit, trellis decoding uses the square of the Euclid distance between received symbols and representative symbols of a subset, and the square of the Euclid distance is used as a branch metric as it is. Also, bits are reduced by imposing amplitude limitations on the received symbol. In addition, bits are truncated at an output of Euclid distance calculation means to reduce the processing and circuit scales.
In a prior art of “Viterbi Decoding Method and Apparatus” in Japanese Patent Laid-open Publication No.10-200419, a path memory update operation and an output operation are simultaneously performed and respective sets of units are alternately operated with shifted phases. Thus, the scale of the path memory is reduced, and the processing and circuit scales are reduced in the Viterbi decoder.
The aforementioned prior art Viterbi decoders have the large processing and circuit scales, and reductions in the scales are problems to be overcome.
In the prior art shown in
FIG. 1
, the metric data of K bits for state N or the inverted metric data of k bits for state N+128 after the latching is selected by time-division switches
28
a
to
28
c
for k bits in accordance with the timing pulses. Therefore, when multiplexers are used, for example, as time-division switches
28
a
to
28
c
for k bits, the configuration for switching k bits is complicated to increase the processing and circuit scales.
For this reason, it is difficult to reduce the processing and circuit scales in control offices and mobil stations in cellular mobile telephone systems of a TDMA scheme, a TDMA/TDD scheme or a CDMA scheme, or satellite stations and ground stations in digital satellite communication, and especially in cellular phones, the prior art has a disadvantage of difficulties in meeting demands for size reduction and multiple functions.
In addition, while the prior arts in the gazettes described above can reduce the pr
Chin Stephen
Foley & Lardner LLP
NEC Corporation
Perilla Jason M.
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