Viterbi decoder for decoding error-correcting encoded informatio

Details Viterbi decoder for decoding error-correcting encoded informatio Viterbi decoder for decoding error-correcting encoded informatio

1993-05-26

1996-04-16

Envall, Jr., Roy N.

Excavating

341 78, 341 94, G06F 1110, H03M 1312, H03M 700, H03M 1300

Patent

active

055090214

ABSTRACT:
A Viterbi decoder includes a branch metric generator, a subset maximum likelihood estimator, an accumulator switch circuit (ACS circuit), a most likely path setter, a first selector, and a path-memory circuit for the purpose of estimating encoding bits of a 4-bit error-correcting encoded information symbol string. The Viterbi decoder also includes a noncoding bit detector, eight j-level shift registers, and a second selector for the purpose of estimating a noncoding bit of the 4-bit error-correcting encoded information symbol string. The j-level shift registers are provided for temporarily holding the output signals of the noncoding bit detector. The second selector is provided for selecting one output signal from the output signals of the j-level shift registers in accordance with the output signal of the selector.

REFERENCES:
patent: 5220570 (1993-06-01), Lou et al.
Ungerboech, G., Channel Coding with Multilevel/Phase Signals, IEEE, Transactions on Information Theory, vol. IT-28, No. 1, pp. 55-67, Jan. 1982.
Aikawa, S., et al., Design Schemes for a High-Speed/Multi-Level Trellis Coded Modulation Viterbi Decoder, Journal of the Electronic Information Communication Society, vol. J73-A, No. 2, pp. 331-340, Feb. 1990.
Aikawa, S., et al., 150 KGate General-Purpose High-Coding-Gain TCM VLSIs for High-Speed Multi-Level QAM Systems, IEEE GLOBECOM, pp. 1963-1967, 1990.

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